| Line 36... |
Line 36... |
int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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unsigned long vpn, ppn;
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unsigned long vpn, ppn;
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extern int mem_cycles;
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extern int mem_cycles;
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|
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP))
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if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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|
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
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| Line 72... |
Line 74... |
for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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|
|
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/* Check if page is cache inhibited */
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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|
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mem_cycles += config.dmmu.hitdelay;
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mem_cycles += config.dmmu.hitdelay;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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