| Line 34... |
Line 34... |
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
unsigned long vpn, ppn;
|
unsigned long vpn, ppn;
|
extern int mem_cycles;
|
|
|
|
if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
|
if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
|
data_ci = (virtaddr >= 0x80000000);
|
data_ci = (virtaddr >= 0x80000000);
|
return virtaddr;
|
return virtaddr;
|
}
|
}
|
| Line 77... |
Line 76... |
setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
|
setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
|
|
|
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
|
|
mem_cycles += config.dmmu.hitdelay;
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
int minlru = config.dmmu.ustates - 1;
|
int minlru = config.dmmu.ustates - 1;
|
| Line 102... |
Line 101... |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
|
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);
|
#endif
|
#endif
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
/* if tlb refill implemented in HW */
|
/* if tlb refill implemented in HW */
|
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
mem_cycles += config.dmmu.missdelay;
|
runtime.sim.mem_cycles += config.dmmu.missdelay;
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
|
|
unsigned long dmmu_translate(unsigned long virtaddr, int write_access)
|
unsigned long dmmu_translate(unsigned long virtaddr, int write_access)
|
