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Line 71... |
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);
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setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.dmmu.ustates - 1;
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int minlru = config.dmmu.nsets - 1;
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int minway = 0;
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int minway = 0;
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dmmu_stats.loads_tlbmiss++;
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dmmu_stats.loads_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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