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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [immu.c] - Diff between revs 997 and 1174

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Rev 997 Rev 1174
Line 104... Line 104...
    runtime.sim.mem_cycles += config.immu.missdelay;
    runtime.sim.mem_cycles += config.immu.missdelay;
    return 0;
    return 0;
  }
  }
}
}
 
 
 
/* DESC: try to find EA -> PA transaltion without changing
 
 *       any of precessor states. if this is not passible gives up
 
 *       (without triggering exceptions)
 
 *
 
 * PRMS: virtaddr  - EA for which to find translation
 
 *
 
 * RTRN: 0         - no IMMU, IMMU disabled or ITLB miss
 
 *       else      - appropriate PA (note it IMMU is not present
 
 *                   PA === EA)
 
 */
 
unsigned long peek_into_itlb(unsigned long virtaddr)
 
{
 
  int set, way = -1;
 
  int i;
 
  unsigned long tagaddr;
 
  unsigned long vpn, ppn;
 
 
 
  if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
 
     return(virtaddr);
 
  }
 
 
 
  /* Which set to check out? */
 
  set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
 
  tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
 
  vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
 
 
 
  /* Scan all ways and try to find a matching way. */
 
  for (i = 0; i < config.immu.nways; i++)
 
    if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
 
        testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
 
      way = i;
 
 
 
  /* Did we find our tlb entry? */
 
  if (way >= 0) { /* Yes, we did. */
 
 
 
    /* Test for page fault */
 
    if (mfspr (SPR_SR) & SPR_SR_SM) {
 
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) {
 
        /* no luck, giving up */
 
        return(0);
 
      }
 
    } else {
 
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) {
 
        /* no luck, giving up */
 
        return(0);
 
      }
 
    }
 
 
 
    ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
 
    return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
 
  }
 
  else {
 
    return(0);
 
  }
 
 
 
  PRINTF("ERR, should never have happened\n");
 
  return(0);
 
}
 
 
 
 
unsigned long immu_translate(unsigned long virtaddr)
unsigned long immu_translate(unsigned long virtaddr)
{
{
  unsigned long phyaddr = immu_simulate_tlb(virtaddr);
  unsigned long phyaddr = immu_simulate_tlb(virtaddr);
 
 
/*  PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
/*  PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/

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