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Rev 196 |
Line 51... |
Line 51... |
config.superscalar = 1;
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config.superscalar = 1;
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config.slp = 1;
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config.slp = 1;
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config.profile = 0;
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config.profile = 0;
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mtspr(SPR_VR, SPR_VR_VER & 0x1200);
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mtspr(SPR_VR, SPR_VR_VER & 0x1200);
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mtspr(SPR_CPUCFGR, SPR_CPUCFGR_OB32S);
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mtspr(SPR_DMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
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mtspr(SPR_IMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
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mtspr(SPR_DCCFGR, (0 << 5) | (7 << 2) | (1 << 0));
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mtspr(SPR_ICCFGR, (0 << 5) | (7 << 2) | (1 << 0));
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mtspr(SPR_DCFGR, SPR_DCFGR_WPCI);
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mtspr(SPR_PCCFGR, 1);
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val = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
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val = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
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SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |
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SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |
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SPR_UPR_PMP | SPR_UPR_TTP;
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SPR_UPR_PMP | SPR_UPR_TTP;
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