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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [sim-config.c] - Diff between revs 212 and 221

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Rev 212 Rev 221
Line 39... Line 39...
        config.uarts[0].rxfile = "/tmp/uart0.rx";
        config.uarts[0].rxfile = "/tmp/uart0.rx";
        config.uarts[0].txfile = "/tmp/uart0.tx";
        config.uarts[0].txfile = "/tmp/uart0.tx";
        config.uarts[0].baseaddr = 0x80000000;
        config.uarts[0].baseaddr = 0x80000000;
        config.uarts[0].jitter = -1; /* Async behavior */
        config.uarts[0].jitter = -1; /* Async behavior */
        config.dmas[0].baseaddr = 0x90000000;
        config.dmas[0].baseaddr = 0x90000000;
        config.ram.startaddr = MEMORY_START;
 
        config.ram.endaddr = MEMORY_START + MEMORY_LEN;
 
        config.simdebug = 0;
        config.simdebug = 0;
        config.profile = 0;
        config.profile = 0;
        config.iprompt = 0;
        config.iprompt = 0;
        config.dependstats = 1;
        config.dependstats = 1;
        config.dependency = 1;
        config.dependency = 1;
Line 52... Line 50...
        config.superscalar = 1;
        config.superscalar = 1;
        config.slp = 1;
        config.slp = 1;
        config.profile = 0;
        config.profile = 0;
 
 
        mtspr(SPR_VR, SPR_VR_VER & 0x1200);
        mtspr(SPR_VR, SPR_VR_VER & 0x1200);
        mtspr(SPR_CPUCFGR, SPR_CPUCFGR_OB32S);
 
        mtspr(SPR_DMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
 
        mtspr(SPR_IMMUCFGR, (0 << 5) | (7 << 2) | (1 << 0));
 
        mtspr(SPR_DCCFGR, (0 << 5) | (7 << 2) | (1 << 0));
 
        mtspr(SPR_ICCFGR, (0 << 5) | (7 << 2) | (1 << 0));
 
        mtspr(SPR_DCFGR, SPR_DCFGR_WPCI);
 
        mtspr(SPR_PCCFGR, 1);
 
 
 
        val = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
        val = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
        SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |
        SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |
        SPR_UPR_PMP | SPR_UPR_TTP;
        SPR_UPR_PMP | SPR_UPR_TTP;
 
 
Line 224... Line 215...
        if (config.bp.btic_sim)
        if (config.bp.btic_sim)
                printf("BTIC simulation on.\n");
                printf("BTIC simulation on.\n");
        else
        else
                printf("BTIC simulation off.\n");
                printf("BTIC simulation off.\n");
        printf("Clock cycle: %d ns\n", config.clkcycle_ns);
        printf("Clock cycle: %d ns\n", config.clkcycle_ns);
        printf("RAM: 0x%x to ", config.ram.startaddr);
        /*printf("RAM: 0x%x to 0x%x (%d KB)\n\n", config.ram.startaddr, config.ram.endaddr);
        printf("0x%x (", config.ram.endaddr);
          (config.ram.endaddr - config.ram.startaddr) / 1024); MM170901 different memory scheme.  */
        printf("%d KB)\n\n", (config.ram.endaddr - config.ram.startaddr) / 1024);
 
        if (config.simdebug)
        if (config.simdebug)
                printf("simdebug on, ");
                printf("simdebug on, ");
        else
        else
                printf("simdebug off, ");
                printf("simdebug off, ");
        if (config.iprompt)
        if (config.iprompt)

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