URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 242 |
Rev 257 |
| Line 21... |
Line 21... |
|
|
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
|
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
|
|
|
#define NR_UARTS 4 /* Number of UARTs simulated */
|
#define NR_UARTS 4 /* Number of UARTs simulated */
|
#define NR_DMAS 1 /* Number of DMA controllers */
|
#define NR_DMAS 1 /* Number of DMA controllers */
|
|
#define NR_ETHERNETS 2 /* Number of Ethernet MACs */
|
#define NONE 0
|
#define NONE 0
|
#define VIRTUAL 1
|
#define VIRTUAL 1
|
#define PHYSICAL 2
|
#define PHYSICAL 2
|
|
|
#define STR_SIZE (256)
|
#define STR_SIZE (256)
|
| Line 55... |
Line 56... |
unsigned long baseaddr;
|
unsigned long baseaddr;
|
unsigned irq;
|
unsigned irq;
|
} dmas[NR_DMAS];
|
} dmas[NR_DMAS];
|
|
|
struct {
|
struct {
|
|
unsigned long baseaddr;
|
|
unsigned dma; /* Which controller is this ethernet "connected" to */
|
|
unsigned tx_channel; /* DMA channel used for TX */
|
|
unsigned rx_channel; /* DMA channel used for RX */
|
|
char *rxfile;
|
|
char *txfile;
|
|
} ethernets[NR_ETHERNETS];
|
|
|
|
struct {
|
char memory_table_file[STR_SIZE]; /* Memory table filename */
|
char memory_table_file[STR_SIZE]; /* Memory table filename */
|
int enable; /* is MC enabled? */
|
int enable; /* is MC enabled? */
|
unsigned POC; /* power on reset configuration register */
|
unsigned POC; /* power on reset configuration register */
|
} mc;
|
} mc;
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.