| Line 27... |
Line 27... |
#define MAX_UARTS 4 /* Max. number of UARTs simulated */
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#define MAX_UARTS 4 /* Max. number of UARTs simulated */
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#define MAX_DMAS 4 /* Max. number of DMA controllers */
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#define MAX_DMAS 4 /* Max. number of DMA controllers */
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#define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */
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#define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */
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#define MAX_GPIOS 4 /* Max. number of GPIO modules */
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#define MAX_GPIOS 4 /* Max. number of GPIO modules */
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#define MAX_MEMORIES 16 /* Max. number of memory devices attached */
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#define MAX_MEMORIES 16 /* Max. number of memory devices attached */
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#define MAX_VGAS 4 /* Max. number of VGAs */
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#define MAX_SBUF_LEN 256 /* Max. length of store buffer */
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#define MAX_SBUF_LEN 256 /* Max. length of store buffer */
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#define STR_SIZE (256)
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#define STR_SIZE (256)
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struct config {
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struct config {
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Line 73... |
unsigned long baseaddr; /* Base address */
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unsigned long baseaddr; /* Base address */
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int irq; /* IRQ of this device */
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int irq; /* IRQ of this device */
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unsigned long base_vapi_id; /* First VAPI ID. GPIO uses 8 consecutive IDs */
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unsigned long base_vapi_id; /* First VAPI ID. GPIO uses 8 consecutive IDs */
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} gpios[MAX_GPIOS];
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} gpios[MAX_GPIOS];
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int nvgas;
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struct {
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unsigned long baseaddr; /* Base address */
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int irq; /* IRQ of this device */
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int refresh_rate; /* Number of clocks per refresh */
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char filename[STR_SIZE]; /* Base file name; suffix of ####.bmp is added */
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} vgas[MAX_VGAS];
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struct {
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int enabled; /* Whether frame buffer is enabled */
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unsigned long bufaddr; /* Base address of frame buffer */
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unsigned long paladdr; /* Base address of palette lookup */
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int refresh_rate; /* Number of clocks per refresh */
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char filename[STR_SIZE]; /* Base file name; suffix of ####.bmp is added */
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} fb;
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struct {
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struct {
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int enabled; /* is MC enabled? */
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int enabled; /* is MC enabled? */
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unsigned long baseaddr; /* Naturally aligned base address */
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unsigned long baseaddr; /* Naturally aligned base address */
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unsigned POC; /* power on reset configuration register */
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unsigned POC; /* power on reset configuration register */
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} mc;
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} mc;
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