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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "except.h"
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#include "except.h"
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#include "tick.h"
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#include "tick.h"
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#include "../cpu/or1k/spr_defs.h"
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#include "spr_defs.h"
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#include "pic.h"
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#include "pic.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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/* For mode 10 only: timer stops until we write into TTCR. */
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/* When did the timer start to count */
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int tt_stopped = 0;
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int cycles_start = 0;
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/* TT Count Register */
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unsigned long ttcr;
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/* TT Mode Register */
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unsigned long ttmr;
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extern int cycles;
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/* Reset. It initializes TTCR register. */
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/* Reset. It initializes TTCR register. */
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void tick_reset()
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void tick_reset()
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{
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{
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if (config.tick.enabled) {
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if (config.sim.verbose)
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if (config.sim.verbose)
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printf("Resetting Tick Timer.\n");
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printf("Resetting Tick Timer.\n");
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mtspr(SPR_TTCR, 0);
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mtspr(SPR_TTCR, 0);
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mtspr(SPR_TTMR, 0);
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mtspr(SPR_TTMR, 0);
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tt_stopped = 0;
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} else
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tt_stopped = 1;
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}
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}
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/* Simulation hook. Must be called every clock cycle to simulate tick
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/* Job handler for tick timer */
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timer. It does internal functional tick timer simulation. */
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void tick_job (int param)
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inline void tick_clock()
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{
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{
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unsigned long ttcr;
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int mode = (ttmr & SPR_TTMR_M) >> 30;
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unsigned long ttmr;
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/*debug (7, "tick_job%i, param %i\n", param, mode);*/
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switch (mode) {
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if (tt_stopped)
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case 1:
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return;
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sprs[SPR_TTCR] = ttcr = 0;
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case 2:
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ttcr = mfspr(SPR_TTCR);
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if (ttmr & SPR_TTMR_IE) {
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ttmr = mfspr(SPR_TTMR);
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if (!(ttmr & SPR_TTMR_M))
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return;
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if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {
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int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */
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if (ttmr & SPR_TTMR_IE)
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setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
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setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
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if ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE)
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except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
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}
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break;
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}
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}
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/* Starts the tick timer. This function is called by a write to ttcr spr register */
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void spr_write_ttcr (unsigned long value)
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{
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unsigned mode = (ttmr & SPR_TTMR_M) >> 30;
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/*debug (7, "ttcr = %08x\n", value);*/
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ttcr = value;
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/* Remove previous if it exists */
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SCHED_FIND_REMOVE(tick_job, 0);
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if (mode == 1 || mode == 2) {
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SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
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cycles_start = cycles - ttcr;
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}
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}
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/* Handle the modes properly.. CZ 04/09/01 */
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void spr_write_ttmr (unsigned long value)
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switch(mode)
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{
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{
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/*debug (7, "ttmr = %08x\n", value);*/
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ttmr = value;
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/* Handle the modes properly. */
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switch((ttmr & SPR_TTMR_M) >> 30) {
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case 0: /* Timer is disabled */
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case 0: /* Timer is disabled */
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tt_stopped = 1;
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break;
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break;
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case 1: /* Timer should auto restart */
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case 1: /* Timer should auto restart */
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ttcr = 0;
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sprs[SPR_TTCR] = ttcr = 0;
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mtspr(SPR_TTCR,ttcr);
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cycles_start = cycles;
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SCHED_FIND_REMOVE(tick_job, 0);
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SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
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break;
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break;
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case 2: /* Pause the timer */
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case 2: /* Stop the timer when match */
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tt_stopped = 1;
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SCHED_FIND_REMOVE(tick_job, 0);
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break;
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break;
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case 3: /* Timer keeps running */
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case 3: /* Timer keeps running -- do nothing*/
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break;
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break;
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}
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}
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}
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}
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if ((ttmr & SPR_TTMR_IP) && ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE))
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unsigned long spr_read_ttcr ()
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except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
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{
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/*debug (7, "ttcr ---- %08x\n", cycles - cycles_start);*/
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if (!tt_stopped)
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return cycles - cycles_start;
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ttcr++;
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mtspr(SPR_TTCR, ttcr);
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}
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}
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No newline at end of file
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No newline at end of file
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