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Line 29... |
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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extern int delay_insn;
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extern oraddr_t pcprev;
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extern oraddr_t pcprev;
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extern oraddr_t pcdelay;
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int except_pending = 0;
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int except_pending = 0;
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static const char *except_names[] = {
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static const char *except_names[] = {
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NULL,
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NULL,
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| Line 73... |
Line 73... |
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if (config.sim.verbose)
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if (config.sim.verbose)
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", cycles %lld, #%lld\n",
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", cycles %lld, #%lld\n",
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except, except_name(except), pcprev, ea, pc, pcnext, pcdelay,
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except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,
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runtime.sim.cycles, runtime.cpu.instructions);
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cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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switch(except) {
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switch(except) {
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/* EPCR is irrelevent */
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/* EPCR is irrelevent */
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Line 93... |
case EXCEPT_ILLEGAL:
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case EXCEPT_ILLEGAL:
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case EXCEPT_DTLBMISS:
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case EXCEPT_DTLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_RANGE:
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case EXCEPT_RANGE:
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case EXCEPT_TRAP:
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case EXCEPT_TRAP:
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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break;
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break;
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/* EPCR is loaded with address of next not-yet-executed instruction */
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/* EPCR is loaded with address of next not-yet-executed instruction */
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case EXCEPT_SYSCALL:
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case EXCEPT_SYSCALL:
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mtspr(SPR_EPCR_BASE, (pc + 4) - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0));
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break;
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break;
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/* These exceptions happen AFTER (or before) an instruction has been
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/* These exceptions happen AFTER (or before) an instruction has been
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* simulated, therefore the pc already points to the *next* instruction */
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* simulated, therefore the pc already points to the *next* instruction */
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case EXCEPT_TICK:
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case EXCEPT_TICK:
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case EXCEPT_INT:
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case EXCEPT_INT:
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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/* If we don't update the pc now, then it will only happen *after* the next
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/* If we don't update the pc now, then it will only happen *after* the next
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* instruction (There would be serious problems if the next instruction just
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* instruction (There would be serious problems if the next instruction just
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* happens to be a branch), when it should happen NOW. */
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* happens to be a branch), when it should happen NOW. */
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pc = pcnext;
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cpu_state.pc = pcnext;
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pcnext += 4;
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pcnext += 4;
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break;
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break;
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}
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}
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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Line 124... |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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delay_insn = 0;
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cpu_state.delay_insn = 0;
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}
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}
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No newline at end of file
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No newline at end of file
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