| Line 36... |
Line 36... |
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/* See also enum insn_type in abstract.h */
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/* See also enum insn_type in abstract.h */
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const char func_unit_str[30][30] = { "unknown", "exception", "arith", "shift", "compare",
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const char func_unit_str[30][30] = { "unknown", "exception", "arith", "shift", "compare",
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"branch", "jump", "load", "store", "movimm", "move", "extend", "nop", "mac" };
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"branch", "jump", "load", "store", "movimm", "move", "extend", "nop", "mac" };
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struct dstats_entry dstats[DSTATS_LEN]; /* dependency stats */
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struct dstats_entry dstats[DSTATS_LEN] = {0}; /* dependency stats */
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struct sstats_entry sstats[SSTATS_LEN]; /* single stats */
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struct sstats_entry sstats[SSTATS_LEN] = {0}; /* single stats */
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struct fstats_entry fstats[FSTATS_LEN]; /* functional units stats */
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struct fstats_entry fstats[FSTATS_LEN] = {0}; /* functional units stats */
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struct mstats_entry mstats; /* misc units stats */
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struct mstats_entry mstats = {0}; /* misc units stats */
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struct cachestats_entry ic_stats; /* instruction cache stats */
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struct cachestats_entry ic_stats = {0}; /* instruction cache stats */
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struct cachestats_entry dc_stats; /* data cache stats */
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struct cachestats_entry dc_stats = {0}; /* data cache stats */
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struct immustats_entry immu_stats; /* insn mmu stats */
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struct immustats_entry immu_stats = {0}; /* insn mmu stats */
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struct dmmustats_entry dmmu_stats; /* data mmu stats */
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struct dmmustats_entry dmmu_stats = {0}; /* data mmu stats */
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struct raw_stats raw_stats; /* RAW hazard stats */
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struct raw_stats raw_stats = {0}; /* RAW hazard stats */
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/* Dependency */
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/* Dependency */
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int check_depend()
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int check_depend()
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{
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{
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| Line 174... |
Line 174... |
if (config.bpb.btic) {
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if (config.bpb.btic) {
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printf("BTIC: hit %d(%d%%), miss %d\n", mstats.btic.hit, (mstats.btic.hit * 100) / SD(mstats.btic.hit + mstats.btic.miss), mstats.btic.miss);
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printf("BTIC: hit %d(%d%%), miss %d\n", mstats.btic.hit, (mstats.btic.hit * 100) / SD(mstats.btic.hit + mstats.btic.miss), mstats.btic.miss);
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} else
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} else
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printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n");
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printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n");
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if (testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (config.ic.enabled) {
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printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss);
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printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss);
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} else
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} else
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printf("No ICache. Set UPR[ICP]\n");
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printf("No ICache. Enable it to see IC results.\n");
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if (testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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if (config.dc.enabled) {
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printf("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss);
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printf("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss);
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printf("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss);
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printf("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss);
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} else
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} else
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printf("No DCache. Set UPR[DCP]\n");
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printf("No DCache. Enable it to see DC results.\n");
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if (testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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printf("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss);
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printf("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss);
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} else
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} else
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printf("No IMMU. Set UPR[IMP]\n");
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printf("No IMMU. Set UPR[IMP]\n");
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