| Line 41... |
Line 41... |
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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static struct dev_16450 uarts[MAX_UARTS]; /* simulation info */
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static struct dev_16450 uarts[MAX_UARTS]; /* simulation info */
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static struct channel * channels[MAX_UARTS] = { NULL, }; /* emulation info */
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static struct channel * channels[MAX_UARTS] = { NULL, }; /* emulation info */
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static int thre_int;
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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before a single character is transmitted or received. */
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before a single character is transmitted or received. */
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static unsigned long char_clks(int dll, int dlh, int lcr)
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static unsigned long char_clks(int dll, int dlh, int lcr)
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{
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{
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| Line 113... |
Line 112... |
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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if (value & UART_FCR_RTXFI) {
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if (value & UART_FCR_RTXFI) {
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uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
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uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
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uarts[chipsel].istat.txbuf_full = 0;
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uarts[chipsel].istat.txbuf_full = 0;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
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uarts[chipsel].istat.thre_int = 0;
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}
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}
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if (value & UART_FCR_RRXFI) {
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if (value & UART_FCR_RRXFI) {
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uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
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uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
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uarts[chipsel].istat.rxbuf_full = 0;
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uarts[chipsel].istat.rxbuf_full = 0;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
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}
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}
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break;
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break;
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case UART_IER:
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case UART_IER:
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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uarts[chipsel].regs.ier = value & UART_VALID_IER;
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#if 0
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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uarts[chipsel].istat.thre_int = 1;
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#endif
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
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break;
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break;
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| Line 361... |
Line 357... |
uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
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uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
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uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
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uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
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uarts[i].istat.txser_full = 1;
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uarts[i].istat.txser_full = 1;
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uarts[i].istat.txbuf_full--;
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uarts[i].istat.txbuf_full--;
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uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
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uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
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// When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
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// the THRE interrupt is raised when THR transitions from full to empty.
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if (!uarts[i].istat.txbuf_full) {
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uarts[i].istat.thre_int = 1;
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uarts[i].istat.thre_int = 1;
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uarts[i].regs.lsr |= UART_LSR_TXBUFE;
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}
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} else {
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} else {
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uarts[i].regs.lsr |= UART_LSR_TXSERE;
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uarts[i].regs.lsr |= UART_LSR_TXSERE;
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uarts[i].regs.lsr |= UART_LSR_TXBUFE;
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}
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}
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} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
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} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
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send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
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send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
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} else {
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} else {
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/* We are still sending char here*/
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/* We are still sending char here*/
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| Line 388... |
Line 389... |
/* mark as character was sent */
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/* mark as character was sent */
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uarts[i].istat.txser_full = 0;
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uarts[i].istat.txser_full = 0;
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uarts[i].istat.txser_clks = 0;
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uarts[i].istat.txser_clks = 0;
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} else
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} else
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uarts[i].vapi.break_sent = 0;
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uarts[i].vapi.break_sent = 0;
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}
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// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
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if (!uarts[i].istat.txbuf_full && (uarts[i].fifo_len == 16)) {
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uarts[i].regs.lsr |= UART_LSR_TXBUFE;
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uarts[i].istat.thre_int = 1;
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}
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}
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/***************** Receive *****************/
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/***************** Receive *****************/
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/* Is there a break? */
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/* Is there a break? */
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| Line 542... |
Line 550... |
uarts[i].regs.iir = UART_IIR_RDI;
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uarts[i].regs.iir = UART_IIR_RDI;
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} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
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} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
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&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
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&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
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uarts[i].regs.iir = UART_IIR_CTI;
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uarts[i].regs.iir = UART_IIR_CTI;
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} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
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} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
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uarts[i].regs.lsr & UART_LSR_TXBUFE &&
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uarts[i].istat.thre_int == 1) {
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uarts[i].istat.thre_int == 1) {
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uarts[i].regs.iir = UART_IIR_THRI;
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uarts[i].regs.iir = UART_IIR_THRI;
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} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
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} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
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uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
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uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
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| UART_MSR_TERI | UART_MSR_DDCD)) {
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| UART_MSR_TERI | UART_MSR_DDCD)) {
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