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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 1145 |
Rev 1153 |
Line 100... |
Line 100... |
uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
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uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
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} else
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} else
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
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uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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if (uarts[chipsel].regs.iir & UART_IIR_THRI)
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_FCR:
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case UART_FCR:
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uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
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uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
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if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
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if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
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Line 196... |
Line 197... |
case UART_IER:
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case UART_IER:
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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value = uarts[chipsel].regs.ier & UART_VALID_IER;
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break;
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break;
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case UART_IIR:
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case UART_IIR:
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value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
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value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
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if (uarts[chipsel].regs.ier & UART_IER_THRI)
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if (uarts[chipsel].regs.iir & UART_IIR_THRI)
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uarts[chipsel].istat.thre_int = 0;
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uarts[chipsel].istat.thre_int = 0;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
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break;
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break;
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