URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_65/] [or1ksim/] [tick/] [tick.c] - Diff between revs 91 and 100

Rev 91	Rev 100
Line 26...	Line 26...
`#include <string.h>`	`#include <string.h>`

`#include "tick.h"`	`#include "tick.h"`
`#include "../cpu/or1k/spr_defs.h"`	`#include "../cpu/or1k/spr_defs.h"`

`static unsigned long timer;`

`/* Reset. It initializes TTCR register. */`	`/* Reset. It initializes TTCR register. */`
`void tick_reset()`	`void tick_reset()`
`{`	`{`
`printf("Resetting Tick Timer.\n");`	`printf("Resetting Tick Timer.\n");`
`mtspr(SPR_TTCR, 0);`	`mtspr(SPR_TTCR, 0);`
	`mtspr(SPR_TTIR, 0);`
`}`	`}`

`/* Simulation hook. Must be called every clock cycle to simulate tick`	`/* Simulation hook. Must be called every clock cycle to simulate tick`
`timer. It does internal functional tick timer simulation. */`	`timer. It does internal functional tick timer simulation. */`
`void tick_clock()`	`void tick_clock()`
`{`	`{`
`unsigned long ttcr;`	`unsigned long ttcr;`
	`unsigned long ttir;`

`ttcr = mfspr(SPR_TTCR);`	`ttcr = mfspr(SPR_TTCR);`
	`ttir = mfspr(SPR_TTIR);`

`if (!(ttcr & SPR_TTCR_TTE))`	`if (!(ttcr & SPR_TTCR_TTE))`
`return;`	`return;`

`if (timer == 0) {`	`if ((ttir & SPR_TTCR_PERIOD) == (ttcr & SPR_TTCR_PERIOD)) {`
`if (!(ttcr & SPR_TTCR_SR))`
`timer = ttcr & SPR_TTCR_PERIOD;`
`if (ttcr & SPR_TTCR_IE) {`	`if (ttcr & SPR_TTCR_IE) {`
`setsprbits(SPR_TTCR, SPR_TTCR_IP, 1);`	`setsprbits(SPR_TTCR, SPR_TTCR_IP, 1);`
`report_interrupt();`	`report_interrupt();`
`}`	`}`
	`if (ttcr & SPR_TTCR_SR)`
	`return;`
`}`	`}`
`if (timer)`	`ttir++;`
`timer--;`	`mtspr(SPR_TTIR, ttir);`

`}`	`}`

`No newline at end of file`	`No newline at end of file`