| Line 71... |
Line 71... |
unsigned long dc_simulate_read(unsigned long dataaddr, int width)
|
unsigned long dc_simulate_read(unsigned long dataaddr, int width)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
extern int mem_cycles;
|
|
unsigned long tmp;
|
unsigned long tmp;
|
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
data_ci) {
|
data_ci) {
|
| Line 102... |
Line 101... |
|
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
mem_cycles += config.dc.load_hitdelay;
|
runtime.sim.mem_cycles += config.dc.load_hitdelay;
|
|
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
if (width == 4)
|
if (width == 4)
|
return tmp;
|
return tmp;
|
else if (width == 2) {
|
else if (width == 2) {
|
| Line 140... |
Line 139... |
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
mem_cycles += config.dc.load_missdelay;
|
runtime.sim.mem_cycles += config.dc.load_missdelay;
|
|
|
tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
if (width == 4)
|
if (width == 4)
|
return tmp;
|
return tmp;
|
else if (width == 2) {
|
else if (width == 2) {
|
| Line 172... |
Line 171... |
void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
|
void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
extern int mem_cycles;
|
|
unsigned long tmp;
|
unsigned long tmp;
|
|
|
if (width == 4)
|
if (width == 4)
|
setsim_mem32(dataaddr, data);
|
setsim_mem32(dataaddr, data);
|
else if (width == 2)
|
else if (width == 2)
|
| Line 205... |
Line 203... |
|
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
mem_cycles += config.dc.store_hitdelay;
|
runtime.sim.mem_cycles += config.dc.store_hitdelay;
|
|
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
if (width == 4)
|
if (width == 4)
|
tmp = data;
|
tmp = data;
|
else if (width == 2) {
|
else if (width == 2) {
|
| Line 245... |
Line 243... |
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
mem_cycles += config.dc.store_missdelay;
|
runtime.sim.mem_cycles += config.dc.store_missdelay;
|
}
|
}
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- invalidate block if way isn't locked
|
- invalidate block if way isn't locked
|
