| Line 97... |
Line 97... |
uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
|
uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
|
uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
|
uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
|
} else
|
} else
|
uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
|
uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
|
|
|
if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len)
|
uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
|
|
else
|
|
uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
|
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
|
|
|
|
uarts[chipsel].istat.thre_int = 0;
|
uarts[chipsel].istat.thre_int = 0;
|
break;
|
break;
|
case UART_FCR:
|
case UART_FCR:
|
uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
|
uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
|
| Line 114... |
Line 110... |
value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
|
value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
|
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
|
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
|
if (value & UART_FCR_RTXFI) {
|
if (value & UART_FCR_RTXFI) {
|
uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
|
uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
|
uarts[chipsel].istat.txbuf_full = 0;
|
uarts[chipsel].istat.txbuf_full = 0;
|
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
|
}
|
}
|
if (value & UART_FCR_RRXFI) {
|
if (value & UART_FCR_RRXFI) {
|
uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
|
uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
|
uarts[chipsel].istat.rxbuf_full = 0;
|
uarts[chipsel].istat.rxbuf_full = 0;
|
|
uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
|
}
|
}
|
break;
|
break;
|
case UART_IER:
|
case UART_IER:
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
uarts[chipsel].istat.thre_int = 0;
|
uarts[chipsel].istat.thre_int = 0;
|
| Line 312... |
Line 310... |
}
|
}
|
uarts[uart].istat.txser_full = 0;
|
uarts[uart].istat.txser_full = 0;
|
uarts[uart].istat.txser_clks = 0;
|
uarts[uart].istat.txser_clks = 0;
|
}
|
}
|
|
|
|
/* Adds a character to the FIFO */
|
|
|
|
void uart_add_char (int uart, int ch)
|
|
{
|
|
if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)
|
|
uarts[uart].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
|
else {
|
|
debug(4, "add %02x\n", ch);
|
|
uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;
|
|
uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;
|
|
uarts[uart].istat.rxbuf_full++;
|
|
}
|
|
uarts[uart].regs.lsr |= UART_LSR_RDRDY;
|
|
uarts[uart].istat.timeout_count = 0;
|
|
}
|
|
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
(re)opens all RX/TX file streams and places devices in memory address
|
(re)opens all RX/TX file streams and places devices in memory address
|
space. */
|
space. */
|
void uart_reset()
|
void uart_reset()
|
{
|
{
|
| Line 385... |
Line 399... |
if (!config.uarts[i].vapi_id && !uarts[i].txfs) continue;
|
if (!config.uarts[i].vapi_id && !uarts[i].txfs) continue;
|
|
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (--uarts[i].vapi.next_break_cnt < 0) {
|
if (--uarts[i].vapi.next_break_cnt < 0) {
|
if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
|
if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
|
uarts[i].regs.lsr &= ~UART_LSR_BREAK;
|
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.break_set = 0;
|
}
|
}
|
|
|
/***************** Transmit *****************/
|
/***************** Transmit *****************/
|
if (!uarts[i].istat.txser_full) {
|
if (!uarts[i].istat.txser_full) {
|
| Line 432... |
Line 445... |
/* Is there a break? */
|
/* Is there a break? */
|
if (uarts[i].vapi.cur_break) {
|
if (uarts[i].vapi.cur_break) {
|
uarts[i].vapi.cur_break_cnt++;
|
uarts[i].vapi.cur_break_cnt++;
|
if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
|
if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
|
if (!uarts[i].istat.break_set) {
|
if (!uarts[i].istat.break_set) {
|
|
unsigned lsr;
|
uarts[i].istat.break_set = 1;
|
uarts[i].istat.break_set = 1;
|
uarts[i].regs.lsr |= UART_LSR_BREAK | UART_LSR_FRAME | UART_LSR_RXERR | UART_LSR_RDRDY;
|
lsr = UART_LSR_BREAK | UART_LSR_FRAME | UART_LSR_RXERR | UART_LSR_RDRDY;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].regs.lsr |= UART_LSR_PARITY;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) lsr |= UART_LSR_PARITY;
|
printf ("[%x]\n", uarts[i].regs.lsr);
|
printf ("[%x]\n", uarts[i].regs.lsr);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
|
uart_add_char (i, lsr << 8);
|
if (uarts[i].istat.rxbuf_full + 1 > uarts[i].fifo_len)
|
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
|
else {
|
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_head] = 0;
|
|
debug(4, "add %02x\n", 0);
|
|
uarts[i].istat.rxbuf_head = (uarts[i].istat.rxbuf_head + 1) % uarts[i].fifo_len;
|
|
uarts[i].istat.rxbuf_full++;
|
|
}
|
|
uarts[i].regs.lsr |= UART_LSR_RDRDY;
|
|
uarts[i].istat.timeout_count = 0;
|
|
} else
|
} else
|
uarts[i].vapi.cur_break_cnt = 0;
|
uarts[i].vapi.cur_break_cnt = 0;
|
}
|
}
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
}
|
}
|
} else {
|
} else {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
|
if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
|
uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1);
|
/* Set unused character bits to zero and allow lsr register in fifo */
|
|
uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) | 0xff00;
|
debug(4, "Receiving 0x%02x'%c' via UART%d...\n", uarts[i].iregs.rxser, uarts[i].iregs.rxser, i);
|
debug(4, "Receiving 0x%02x'%c' via UART%d...\n", uarts[i].iregs.rxser, uarts[i].iregs.rxser, i);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
|
uart_add_char (i, uarts[i].iregs.rxser);
|
if (uarts[i].istat.rxbuf_full + 1 > uarts[i].fifo_len)
|
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
|
else {
|
|
debug(4, "add %02x\n", uarts[i].iregs.rxser);
|
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_head] = uarts[i].iregs.rxser;
|
|
uarts[i].istat.rxbuf_head = (uarts[i].istat.rxbuf_head + 1) % uarts[i].fifo_len;
|
|
uarts[i].istat.rxbuf_full++;
|
|
}
|
|
uarts[i].regs.lsr |= UART_LSR_RDRDY;
|
|
uarts[i].istat.timeout_count = 0;
|
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Check if there is something waiting, and put it into rxser */
|
/* Check if there is something waiting, and put it into rxser */
|
| Line 501... |
Line 496... |
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
switch (data >> 24) {
|
switch (data >> 24) {
|
case 0x00:
|
case 0x00:
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
/* Put data into rx fifo */
|
/* Put data into rx fifo */
|
|
uarts[i].iregs.rxser = data & 0xff;
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
|
if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
|
|| uarts[i].vapi.char_clks != uarts[i].char_clks
|
|| uarts[i].vapi.char_clks != uarts[i].char_clks
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
|
uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
|
/* Set error bits */
|
/* Set error bits */
|
uarts[i].regs.lsr |= UART_LSR_FRAME | UART_LSR_RXERR;
|
uarts[i].iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].regs.lsr |= UART_LSR_PARITY;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser |= UART_LSR_PARITY << 8;
|
}
|
}
|
uarts[i].iregs.rxser = data & 0xff;
|
|
uarts[i].istat.rxser_full = 1;
|
uarts[i].istat.rxser_full = 1;
|
received = 1;
|
received = 1;
|
break;
|
break;
|
case 0x01:
|
case 0x01:
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
| Line 564... |
Line 559... |
}
|
}
|
|
|
if (uarts[i].regs.lsr & UART_LSR_RDRDY)
|
if (uarts[i].regs.lsr & UART_LSR_RDRDY)
|
uarts[i].istat.timeout_count++;
|
uarts[i].istat.timeout_count++;
|
|
|
|
/* Update LSR error bits from the ones from rx FIFO */
|
|
if (uarts[i].istat.rxbuf_full) {
|
|
uarts[i].regs.lsr |= uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] >> 8;
|
|
/* we must delete the lsr status, so that we can clear it from lsr */
|
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] &= 0xff;
|
|
}
|
|
|
/* Interrupt detection in proper priority order. */
|
/* Interrupt detection in proper priority order. */
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
if (uarts[i].regs.ier & UART_IER_RLSI && /* Receiver LS */
|
if (uarts[i].regs.ier & UART_IER_RLSI && /* Receiver LS */
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
