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Line 49... |
#include "gdbcomm.h"
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#include "gdbcomm.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "coff.h"
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#include "coff.h"
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/* CVS revision number. */
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/* CVS revision number. */
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const char rcsrev[] = "$Revision: 1.69 $";
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const char rcsrev[] = "$Revision: 1.70 $";
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/* Continuos run versus single step tracing switch. */
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/* Continuos run versus single step tracing switch. */
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int cont_run;
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int cont_run;
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/* History of execution */
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/* History of execution */
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Line 660... |
at the end of the cycle; no sim originated memory accesses should be
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at the end of the cycle; no sim originated memory accesses should be
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performed inbetween. */
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performed inbetween. */
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mem_cycles = 0;
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mem_cycles = 0;
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (cont_run > 0) cont_run--;
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if (cont_run > 0) cont_run--;
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pic_clock ();
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if (cpu_clock ()) break;
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if (config.dc.enabled) dc_clock();
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if (config.ic.enabled) ic_clock();
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if (config.pm.enabled) {
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if (config.pm.enabled) {
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if (!testsprbits(SPR_PMR, SPR_PMR_SME))
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if (!testsprbits(SPR_PMR, SPR_PMR_SME))
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IFF (config.tick.enabled) tick_clock();
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IFF (config.tick.enabled) tick_clock();
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} else
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} else
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IFF (config.tick.enabled) tick_clock();
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IFF (config.tick.enabled) tick_clock();
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pic_clock ();
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if (cpu_clock ()) break;
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if (config.dc.enabled) dc_clock();
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if (config.ic.enabled) ic_clock();
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}
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}
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if (config.pm.enabled) pm_clock();
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if (config.pm.enabled) pm_clock();
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if (config.uarts) uart_clock();
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if (config.uarts) uart_clock();
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if (config.dmas) dma_clock();
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if (config.dmas) dma_clock();
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