URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_67/] [or1ksim/] [sim.cfg] - Diff between revs 384 and 388

Rev 384	Rev 388
Line 168...	Line 168...

`upr =`	`upr =`
`changes the upr register`	`changes the upr register`

`superscalar = 0/1`	`superscalar = 0/1`
	`whether CPU is scalar or superscalar`
	`(modify cpu/or32/execute.c to tune superscalar model)`

`hazards = 0/1`	`hazards = 0/1`
	`whether data hazards are tracked in superscalar CPU`
	`and displayed by the simulator r command`

`history = 0/1`	`history = 0/1`
	`whether instruction execution flow is tracked for`
	`display by simulator hist command. Useful for`
	`back-trace debugging.`

`dependstats = 0/1`	`dependstats = 0/1`
	`whether inter-instruction dependencies are calculated`
	`and displayed by simulator stats command.`

`dependency = 0/1`	`dependency = 0/1`
	`whether inter-instruction dependencies are calculated`
	`and displayed by simulator stats command.`

`slp = 0/1`	`slp = 0/1`
	`calculation of subroutine level parallelism. Displayed`
	`by simulator stats command.`

`btic = 0/1`	`btic = 0/1`
	`enable branch target instruction cache model`

`bpb = 0/1`	`bpb = 0/1`
	`enable branch prediction buffer model`

`parameters for CPU analysis`	`parameters for CPU analysis`
`*/`	`*/`

`section cpu`	`section cpu`
`ver = 0x1200`	`ver = 0x1200`
`rev = 0x0001`	`rev = 0x0001`
`/* upr = */`	`/* upr = */`
`superscalar = 0`	`superscalar = 0`
`hazards = 0`	`hazards = 0`
`history = 0`	`history = 1`
`dependstats = 0`	`dependstats = 0`
`dependency = 0`	`dependency = 0`
`slp = 0`	`slp = 0`
`btic = 0`	`btic = 0`
`bpb = 0`	`bpb = 0`