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Line 53... |
/* MEMORY SECTION
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/* MEMORY SECTION
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This section specifies how is initial memory generated and which blocks
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This section specifies how is initial memory generated and which blocks
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it consist of.
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it consist of.
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memory_table_file = ""
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loads memory table from filename. If filename does not exists in the
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current directory, it is loaded from ~/.or1k/.
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Memory table file structure is as follows:
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>start_address1 length1 type1 [ce1 [delayr1 [delayw1]]]
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>start_address2 length2 type2 [ce2 [delayr2 [delayw2]]]
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>start_address3 length3 type3 [ce3 [delayr3 [delayw3]]]
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(each line start with '>')
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Example:
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>00000100 00001F00 flash 3 100
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>80000000 00010000 RAM
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type = random/unknown/pattern
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type = random/unknown/pattern
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specifies the initial memory values. 'random' parameter generate
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specifies the initial memory values. 'random' parameter generate
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random memory using seed 'random_seed' parameter. 'pattern' parameter
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random memory using seed 'random_seed' parameter. 'pattern' parameter
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fills memory with 'pattern' parameter and 'unknown' does not specify
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fills memory with 'pattern' parameter and 'unknown' does not specify
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how memory should be generated - the fastest option.
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how memory should be generated - the fastest option.
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random_seed =
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random_seed =
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random seed for randomizer, used if type = random
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random seed for randomizer, used if type = random
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pattern =
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pattern =
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pattern to fill memory, used if type = pattern
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pattern to fill memory, used if type = pattern
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nmemories =
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number of memory instances connected
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instance specific:
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baseaddr =
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memory start address
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size =
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memory size
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name = ""
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memory block name
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ce =
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chip enable index of the memory instance
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delayr =
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cycles, required for read access, -1 if instance does not support reading
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delayw =
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cycles, required for write access, -1 if instance does not support writing
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16550 = 0/1
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0, if this device is uart 16450 and 1, if it is 16550
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log = ""
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filename, where to log memory accesses to, no log, if log command is not specified
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*/
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*/
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section memory
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section memory
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memory_table_file = "simmem.cfg"
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/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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nmemories = 2
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device 0
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name = "RAM"
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ce = 0
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baseaddr = 0x00000000
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size = 0x00100000
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delayr = 10
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delayw = -1
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enddevice
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device 1
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name = "FLASH"
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ce = 1
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baseaddr = 0x40000000
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size = 0x00100000
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delayr = 2
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delayw = 4
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enddevice
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end
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end
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/* SIM SECTION
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/* SIM SECTION
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