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/* sim.cfg -- Simulator configuration script file
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/* sim.cfg -- Simulator configuration script file
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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It contains the default configuration and help about configuring
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It contains the default configuration and help about configuring
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the simulator.
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the simulator.
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dev_file1 = ""
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dev_file1 = ""
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dev_size1 = 0
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dev_size1 = 0
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dev_packet1 = 0
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dev_packet1 = 0
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enddevice
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enddevice
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end
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end
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/* CUC SECTION
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This section configures the OpenRISC Custom Unit Compiler
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memory_order = none/weak/strong/exact
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none different memory ordering, even if there are dependencies,
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burst can be made, width can change
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weak different memory ordering, if there cannot be dependencies
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burst can be made, width can change
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strong same memory ordering, burst can be made, width can change
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exact exacltly the same memory ordering and widths
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calling_convention = 0/1
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whether programs follow OpenRISC calling conventions
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enable_bursts = 0/1
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whether burst are detected
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no_multicycle = 0/1
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if selected no multicycle logic paths will be generated
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timings_fn = ""
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*/
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section cuc
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memory_order = weak
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calling_convention = 1
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enable_bursts = 1
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no_multicycle = 1
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timings_fn = "virtex.tim"
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end
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