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[/] [or1k/] [tags/] [nog_patch_67/] [or1ksim/] [testbench/] [mmu.c] - Diff between revs 1024 and 1446

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Rev 1024 Rev 1446
Line 843... Line 843...
  unsigned long ea, ta;
  unsigned long ea, ta;
 
 
  /* Disable IMMU */
  /* Disable IMMU */
  immu_disable();
  immu_disable();
 
 
  /* Invalidate all entries in DTLB */
  /* Invalidate all entries in ITLB */
  for (i = 0; i < ITLB_WAYS; i++) {
  for (i = 0; i < ITLB_WAYS; i++) {
    for (j = 0; j < ITLB_SETS; j++) {
    for (j = 0; j < ITLB_SETS; j++) {
      mtspr (SPR_ITLBMR_BASE(i) + j, 0);
      mtspr (SPR_ITLBMR_BASE(i) + j, 0);
      mtspr (SPR_ITLBTR_BASE(i) + j, 0);
      mtspr (SPR_ITLBTR_BASE(i) + j, 0);
    }
    }
Line 859... Line 859...
    ta = FLASH_START + (i*PAGE_SIZE);
    ta = FLASH_START + (i*PAGE_SIZE);
    mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
    mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
    mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
    mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
  }
  }
 
 
  /* Set dtlb permisions */
  /* Set itlb permisions */
  itlb_val = ITLB_PR_NOLIMIT;
  itlb_val = ITLB_PR_NOLIMIT;
 
 
  /* Write test program */
  /* Write test program */
  for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
  for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
    copy_jump (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
    copy_jump (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
Line 1093... Line 1093...
  return 0;
  return 0;
}
}
 
 
/* Permission test
/* Permission test
   Set various permissions, perform r/w access
   Set various permissions, perform r/w access
   in user and supervisor mode and chack triggering
   in user and supervisor mode and check triggering
   of page fault exceptions */
   of page fault exceptions */
int itlb_premission_test (int set)
int itlb_premission_test (int set)
{
{
  int i, j;
  int i, j;
  unsigned long ea, ta;
  unsigned long ea, ta;

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