URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_67/] [or1ksim/] [toplevel.c] - Diff between revs 1375 and 1387

Rev 1375	Rev 1387
Line 66...	Line 66...
`#include "dumpverilog.h"`	`#include "dumpverilog.h"`
`#include "trace.h"`	`#include "trace.h"`
`#include "cuc.h"`	`#include "cuc.h"`

`/* CVS revision number. */`	`/* CVS revision number. */`
`const char rcsrev[] = "$Revision: 1.116 $";`	`const char rcsrev[] = "$Revision: 1.117 $";`

`inline void debug(int level, const char *format, ...)`	`inline void debug(int level, const char *format, ...)`
`{`	`{`
`char *p;`	`char *p;`
`va_list ap;`	`va_list ap;`
Line 417...	Line 417...
`at the end of the cycle; no sim originated memory accesses should be`	`at the end of the cycle; no sim originated memory accesses should be`
`performed inbetween. */`	`performed inbetween. */`
`runtime.sim.mem_cycles = 0;`	`runtime.sim.mem_cycles = 0;`
`if (!config.pm.enabled \|\| !testsprbits(SPR_PMR, SPR_PMR_DME \| SPR_PMR_SME)) {`	`if (!config.pm.enabled \|\| !testsprbits(SPR_PMR, SPR_PMR_DME \| SPR_PMR_SME)) {`
`if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;`	`if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;`
`pic_clock ();`
`if (cpu_clock ()) break;`	`if (cpu_clock ()) break;`
`if (config.dc.enabled) dc_clock();`	`if (config.dc.enabled) dc_clock();`
`if (config.ic.enabled) ic_clock();`	`if (config.ic.enabled) ic_clock();`
`}`	`}`