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[/] [or1k/] [tags/] [nog_patch_68/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 1432 and 1446

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Rev 1432 Rev 1446
Line 45... Line 45...
#include "spr_defs.h"
#include "spr_defs.h"
#include "execute.h"
#include "execute.h"
#include "sprs.h"
#include "sprs.h"
#include "support/profile.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dmmu.h"
 
#include "immu.h"
#include "dcache_model.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "debug.h"
#include "stats.h"
#include "stats.h"
 
 
Line 755... Line 756...
  }
  }
}
}
 
 
/* Set mem, 32-bit. Big endian version.
/* Set mem, 32-bit. Big endian version.
 *
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
 *                 where this instruction is used for patching memory,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 *                 be decided)
 */
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
Line 845... Line 846...
  if (config.debug.enabled) {
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
  }
 
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
  dc_simulate_write(memaddr, value, 2);
 
 
  if (cur_area && cur_area->log)
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
             value);
}
}

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