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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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/* Bit results with SPR_DCR_CC mask */
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/* Bit results with SPR_DCR_CC mask */
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_EQUAL 0x00000001
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#define SPR_DCR_CC_EQUAL 0x00000002
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#define SPR_DCR_CC_LESS 0x00000002
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#define SPR_DCR_CC_LESS 0x00000004
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#define SPR_DCR_CC_LESSE 0x00000003
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#define SPR_DCR_CC_LESSE 0x00000006
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#define SPR_DCR_CC_GREAT 0x00000004
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#define SPR_DCR_CC_GREAT 0x00000008
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#define SPR_DCR_CC_GREATE 0x00000005
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#define SPR_DCR_CC_GREATE 0x0000000a
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#define SPR_DCR_CC_NEQUAL 0x00000006
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#define SPR_DCR_CC_NEQUAL 0x0000000c
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/* Bit results with SPR_DCR_CT mask */
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/* Bit results with SPR_DCR_CT mask */
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_LSEA 0x000000c0
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#define SPR_DCR_CT_LSEA 0x000000c0
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#define SPR_DCR_CT_LSD 0x000000e0
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/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
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/*
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/*
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* Bit definitions for Debug Mode 1 register
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* Bit definitions for Debug Mode 1 register
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*
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*
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*/
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*/
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