URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 1153 |
Rev 1165 |
Line 544... |
Line 544... |
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* RD available */
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* RD available */
|
&& (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
|
&& (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
|
&& (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
|
&& (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
|
uarts[i].regs.iir = UART_IIR_RDI;
|
uarts[i].regs.iir = UART_IIR_RDI;
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
|
&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
|
&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)
|
|
&& (uarts[i].istat.rxbuf_head != uarts[i].istat.rxbuf_tail)) {
|
uarts[i].regs.iir = UART_IIR_CTI;
|
uarts[i].regs.iir = UART_IIR_CTI;
|
} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
|
} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].regs.iir = UART_IIR_THRI;
|
uarts[i].regs.iir = UART_IIR_THRI;
|
} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
|
} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.