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[/] [or1k/] [tags/] [nog_patch_68/] [or1ksim/] [pic/] [pic.c] - Diff between revs 1387 and 1426

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Rev 1387 Rev 1426
Line 36... Line 36...
#include "abstract.h"
#include "abstract.h"
#include "pic.h"
#include "pic.h"
#include "spr_defs.h"
#include "spr_defs.h"
#include "except.h"
#include "except.h"
#include "sprs.h"
#include "sprs.h"
#include "debug.h"
 
#include "sched.h"
#include "sched.h"
 
#include "debug.h"
 
 
extern int cont_run;
extern int cont_run;
 
DEFAULT_DEBUG_CHANNEL(pic);
 
 
/* Reset. It initializes PIC registers. */
/* Reset. It initializes PIC registers. */
void pic_reset()
void pic_reset()
{
{
  PRINTF("Resetting PIC.\n");
  PRINTF("Resetting PIC.\n");
  mtspr(SPR_PICMR, 0);
  mtspr(SPR_PICMR, 0);
  mtspr(SPR_PICPR, 0);
  mtspr(SPR_PICPR, 0);
  mtspr(SPR_PICSR, 0);
  mtspr(SPR_PICSR, 0);
}
}
 
 
/* Simulation hook.  Called when interrupts are masked. */
/* Handles the reporting of an interrupt if it had to be delayed */
void pic_clock(int i)
void pic_clock(void *dat)
{
{
  /* Don't do anything if interrupts not currently enabled */
  /* Don't do anything if interrupts not currently enabled */
  if(testsprbits (SPR_SR, SPR_SR_IEE))
  if(testsprbits (SPR_SR, SPR_SR_IEE))
    except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
    except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
  else
  else
    SCHED_ADD(pic_clock, 0, 1);
    SCHED_ADD(pic_clock, NULL, 1);
}
}
 
 
/* WARNING: Don't eaven try and call this function *during* a simulated
/* WARNING: Don't eaven try and call this function *during* a simulated
 * instruction!! (as in during a read_mem or write_mem callback).  except_handle
 * instruction!! (as in during a read_mem or write_mem callback).  except_handle
 * assumes that this is the case, it breaks otherwise. */
 * assumes that this is the case, it breaks otherwise. */
Line 69... Line 70...
void report_interrupt(int line)
void report_interrupt(int line)
{
{
  setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
  setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
  setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
  setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
 
 
  debug(4, "Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
  TRACE("Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
 
 
  if (getsprbit(SPR_PICMR, line) || line < 2) {
  if (getsprbit(SPR_PICMR, line) || line < 2) {
    setsprbit(SPR_PICSR, line, 1);
    setsprbit(SPR_PICSR, line, 1);
    /* Don't do anything if interrupts not currently enabled */
    /* Don't do anything if interrupts not currently enabled */
    if (testsprbits (SPR_SR, SPR_SR_IEE))
    if (testsprbits (SPR_SR, SPR_SR_IEE)) {
      except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
      except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
    else
      TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
 
    } else
      /* Interrupts not currently enabled, retry next clock cycle */
      /* Interrupts not currently enabled, retry next clock cycle */
      SCHED_ADD(pic_clock, 0, runtime.sim.cycles + 1);
      SCHED_ADD(pic_clock, NULL, 1);
  }
  }
}
}
 
 
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