| Line 72... |
Line 72... |
config.memory.table[i].ce = -1; /* memory is disabled by default */
|
config.memory.table[i].ce = -1; /* memory is disabled by default */
|
}
|
}
|
|
|
/* IMMU & DMMU*/
|
/* IMMU & DMMU*/
|
config.immu.enabled = 0;
|
config.immu.enabled = 0;
|
|
config.immu.hitdelay = 0;
|
|
config.immu.missdelay = 0;
|
config.dmmu.enabled = 0;
|
config.dmmu.enabled = 0;
|
|
config.dmmu.hitdelay = 0;
|
|
config.dmmu.missdelay = 0;
|
|
|
/* IC & DC */
|
/* IC & DC */
|
config.ic.enabled = 0;
|
config.ic.enabled = 0;
|
config.ic.tagtype = CT_PHYSICAL/*CT_VIRTUAL*/;
|
config.ic.tagtype = CT_PHYSICAL/*CT_VIRTUAL*/;
|
|
config.ic.hitdelay = 0;
|
|
config.ic.missdelay = 0;
|
config.dc.enabled = 0;
|
config.dc.enabled = 0;
|
config.dc.tagtype = CT_PHYSICAL/*CT_VIRTUAL*/;
|
config.dc.tagtype = CT_PHYSICAL/*CT_VIRTUAL*/;
|
|
config.dc.load_hitdelay = 0;
|
|
config.dc.load_missdelay = 0;
|
|
config.dc.store_hitdelay = 0;
|
|
config.dc.store_missdelay = 0;
|
|
|
/* Memory Controller */
|
/* Memory Controller */
|
config.mc.enabled = 0;
|
config.mc.enabled = 0;
|
|
|
/* Uarts */
|
/* Uarts */
|
| Line 260... |
Line 270... |
printf("No data cache.\n");
|
printf("No data cache.\n");
|
if (testsprbits(SPR_UPR, SPR_UPR_ICP))
|
if (testsprbits(SPR_UPR, SPR_UPR_ICP))
|
printf("Insn cache tag: %s\n", config.ic.tagtype == CT_VIRTUAL ? "virtual" : "physical");
|
printf("Insn cache tag: %s\n", config.ic.tagtype == CT_VIRTUAL ? "virtual" : "physical");
|
else
|
else
|
printf("No instruction cache.\n");
|
printf("No instruction cache.\n");
|
if (config.cpu.bpb)
|
if (config.bpb.enabled)
|
printf("BPB simulation on.\n");
|
printf("BPB simulation on.\n");
|
else
|
else
|
printf("BPB simulation off.\n");
|
printf("BPB simulation off.\n");
|
if (config.cpu.btic)
|
if (config.bpb.btic)
|
printf("BTIC simulation on.\n");
|
printf("BTIC simulation on.\n");
|
else
|
else
|
printf("BTIC simulation off.\n");
|
printf("BTIC simulation off.\n");
|
}
|
}
|
}
|
}
|
| Line 347... |
Line 357... |
{"?", 0}, /* 0 */
|
{"?", 0}, /* 0 */
|
{"mc", 0},
|
{"mc", 0},
|
{"uart", 0},
|
{"uart", 0},
|
{"dma", 0},
|
{"dma", 0},
|
{"memory", 0},
|
{"memory", 0},
|
{"cpu", 0},
|
{"cpu", 0}, /* 5 */
|
{"sim", 0},
|
{"sim", 0},
|
{"debug", 0},
|
{"debug", 0},
|
{"VAPI", 0},
|
{"VAPI", 0},
|
{"ethernet",0},
|
{"ethernet",0},
|
{"tick", 0}, /* 10 */
|
{"tick", 0}, /* 10 */
|
{"immu", 0},
|
{"immu", 0},
|
{"dmmu", 0},
|
{"dmmu", 0},
|
{"ic", 0},
|
{"ic", 0},
|
{"dc", 0},
|
{"dc", 0},
|
{"gpio", 0}
|
{"gpio", 0}, /* 15 */
|
|
{"bpb", 0}
|
};
|
};
|
|
|
/* *INDENT-OFF* */
|
/* *INDENT-OFF* */
|
|
|
/* Parameter definitions */
|
/* Parameter definitions */
|
| Line 415... |
Line 426... |
{5, 0, "rev", "=0x%x", NULL, (void *)(&config.cpu.rev)},
|
{5, 0, "rev", "=0x%x", NULL, (void *)(&config.cpu.rev)},
|
{5, 0, "upr", "=0x%x", NULL, (void *)(&config.cpu.upr)},
|
{5, 0, "upr", "=0x%x", NULL, (void *)(&config.cpu.upr)},
|
{5, 0, "hazards", "=%i", NULL, (void *)(&config.cpu.hazards)},
|
{5, 0, "hazards", "=%i", NULL, (void *)(&config.cpu.hazards)},
|
{5, 0, "superscalar", "=%i", NULL, (void *)(&config.cpu.superscalar)},
|
{5, 0, "superscalar", "=%i", NULL, (void *)(&config.cpu.superscalar)},
|
{5, 0, "dependstats", "=%i", NULL, (void *)(&config.cpu.dependstats)},
|
{5, 0, "dependstats", "=%i", NULL, (void *)(&config.cpu.dependstats)},
|
{5, 0, "sbp_bnf_fwd", "=%i", NULL, (void *)(&config.cpu.sbp_bnf_fwd)},
|
|
{5, 0, "sbp_bf_fwd", "=%i", NULL, (void *)(&config.cpu.sbp_bf_fwd)},
|
|
{5, 0, "raw_range", "=%i", cpu_raw_range, (void *)(&config.cpu.raw_range)},
|
{5, 0, "raw_range", "=%i", cpu_raw_range, (void *)(&config.cpu.raw_range)},
|
{5, 0, "bpb", "=%i", NULL, (void *)(&config.cpu.bpb)},
|
|
{5, 0, "btic", "=%i", NULL, (void *)(&config.cpu.btic)},
|
|
|
|
{6, 0, "debug", "=%i", NULL, (void *)(&config.sim.debug)},
|
{6, 0, "debug", "=%i", NULL, (void *)(&config.sim.debug)},
|
{6, 0, "iprompt", "=%i", NULL, (void *)(&config.sim.iprompt)},
|
{6, 0, "iprompt", "=%i", NULL, (void *)(&config.sim.iprompt)},
|
{6, 0, "verbose", "=%i", NULL, (void *)(&config.sim.verbose)},
|
{6, 0, "verbose", "=%i", NULL, (void *)(&config.sim.verbose)},
|
{6, 0, "profile", "=%i", NULL, (void *)(&config.sim.profile)},
|
{6, 0, "profile", "=%i", NULL, (void *)(&config.sim.profile)},
|
| Line 463... |
Line 470... |
{11,0, "nsets", "=%i", immu_nsets, (void *)(&tempL)},
|
{11,0, "nsets", "=%i", immu_nsets, (void *)(&tempL)},
|
{11,0, "nways", "=%i", immu_nways, (void *)(&tempL)},
|
{11,0, "nways", "=%i", immu_nways, (void *)(&tempL)},
|
{11,0, "pagesize", "=%i", immu_pagesize, (void *)(&tempL)},
|
{11,0, "pagesize", "=%i", immu_pagesize, (void *)(&tempL)},
|
{11,0, "entrysize", "=%i", immu_entrysize,(void *)(&tempL)},
|
{11,0, "entrysize", "=%i", immu_entrysize,(void *)(&tempL)},
|
{11,0, "ustates", "=%i", immu_ustates, (void *)(&tempL)},
|
{11,0, "ustates", "=%i", immu_ustates, (void *)(&tempL)},
|
|
{11,0, "missdelay", "=%i", NULL, (void *)(&config.immu.missdelay)},
|
|
{11,0, "hitdelay", "=%i", NULL, (void *)(&config.immu.hitdelay)},
|
|
|
{12,0, "enabled", "=%i", dmmu_enabled, (void *)(&tempL)},
|
{12,0, "enabled", "=%i", dmmu_enabled, (void *)(&tempL)},
|
{12,0, "nsets", "=%i", dmmu_nsets, (void *)(&tempL)},
|
{12,0, "nsets", "=%i", dmmu_nsets, (void *)(&tempL)},
|
{12,0, "nways", "=%i", dmmu_nways, (void *)(&tempL)},
|
{12,0, "nways", "=%i", dmmu_nways, (void *)(&tempL)},
|
{12,0, "pagesize", "=%i", dmmu_pagesize, (void *)(&tempL)},
|
{12,0, "pagesize", "=%i", dmmu_pagesize, (void *)(&tempL)},
|
{12,0, "entrysize", "=%i", dmmu_entrysize,(void *)(&tempL)},
|
{12,0, "entrysize", "=%i", dmmu_entrysize,(void *)(&tempL)},
|
{12,0, "ustates", "=%i", dmmu_ustates, (void *)(&tempL)},
|
{12,0, "ustates", "=%i", dmmu_ustates, (void *)(&tempL)},
|
|
{12,0, "missdelay", "=%i", NULL, (void *)(&config.dmmu.missdelay)},
|
|
{12,0, "hitdelay", "=%i", NULL, (void *)(&config.dmmu.hitdelay)},
|
|
|
{13,0, "enabled", "=%i", ic_enabled, (void *)(&tempL)},
|
{13,0, "enabled", "=%i", ic_enabled, (void *)(&tempL)},
|
{13,0, "nsets", "=%i", ic_nsets, (void *)(&tempL)},
|
{13,0, "nsets", "=%i", ic_nsets, (void *)(&tempL)},
|
{13,0, "nways", "=%i", ic_nways, (void *)(&tempL)},
|
{13,0, "nways", "=%i", ic_nways, (void *)(&tempL)},
|
{13,0, "blocksize", "=%i", ic_blocksize, (void *)(&tempL)},
|
{13,0, "blocksize", "=%i", ic_blocksize, (void *)(&tempL)},
|
{13,0, "ustates", "=%i", ic_ustates, (void *)(&tempL)},
|
{13,0, "ustates", "=%i", ic_ustates, (void *)(&tempL)},
|
{13,0, "tagtype", "=%s ", ic_tagtype, (void *)(&tempS)},
|
{13,0, "tagtype", "=%s ", ic_tagtype, (void *)(&tempS)},
|
|
{13,0, "missdelay", "=%i", NULL, (void *)(&config.ic.missdelay)},
|
|
{13,0, "hitdelay", "=%i", NULL, (void *)(&config.ic.hitdelay)},
|
|
|
{14,0, "enabled", "=%i", dc_enabled, (void *)(&tempL)},
|
{14,0, "enabled", "=%i", dc_enabled, (void *)(&tempL)},
|
{14,0, "nsets", "=%i", dc_nsets, (void *)(&tempL)},
|
{14,0, "nsets", "=%i", dc_nsets, (void *)(&tempL)},
|
{14,0, "nways", "=%i", dc_nways, (void *)(&tempL)},
|
{14,0, "nways", "=%i", dc_nways, (void *)(&tempL)},
|
{14,0, "blocksize", "=%i", dc_blocksize, (void *)(&tempL)},
|
{14,0, "blocksize", "=%i", dc_blocksize, (void *)(&tempL)},
|
{14,0, "ustates", "=%i", dc_ustates, (void *)(&tempL)},
|
{14,0, "ustates", "=%i", dc_ustates, (void *)(&tempL)},
|
{14,0, "tagtype", "=%s ", dc_tagtype, (void *)(&tempS)},
|
{14,0, "tagtype", "=%s ", dc_tagtype, (void *)(&tempS)},
|
|
{14,0, "load_missdelay", "=%i", NULL, (void *)(&config.dc.load_missdelay)},
|
|
{14,0, "load_hitdelay", "=%i", NULL, (void *)(&config.dc.load_hitdelay)},
|
|
{14,0, "store_missdelay", "=%i", NULL, (void *)(&config.dc.store_missdelay)},
|
|
{14,0, "store_hitdelay", "=%i", NULL, (void *)(&config.dc.store_hitdelay)},
|
|
|
{15,0, "enabled", "=%i", NULL, (void *)(&config.gpios_enabled)},
|
{15,0, "enabled", "=%i", NULL, (void *)(&config.gpios_enabled)},
|
{15,0, "ngpios", "=%i", gpio_ngpios, (void *)(&tempL)},
|
{15,0, "ngpios", "=%i", gpio_ngpios, (void *)(&tempL)},
|
{15,0, "device", "%i", change_device, (void *)(&tempL)},
|
{15,0, "device", "%i", change_device, (void *)(&tempL)},
|
{15,0, "baseaddr", "=0x%x", gpio_baseaddr, (void *)(&tempUL)},
|
{15,0, "baseaddr", "=0x%x", gpio_baseaddr, (void *)(&tempUL)},
|
{15,0, "irq", "=%i", gpio_irq, (void *)(&tempL)},
|
{15,0, "irq", "=%i", gpio_irq, (void *)(&tempL)},
|
{15,0, "base_vapi_id", "=0x%x", gpio_base_vapi_id, (void *)(&tempUL)},
|
{15,0, "base_vapi_id", "=0x%x", gpio_base_vapi_id, (void *)(&tempUL)},
|
{15, 0, "enddevice", "", end_device, NULL}
|
{15, 0, "enddevice", "", end_device, NULL},
|
|
|
|
{16, 0, "enabled", "=%i", NULL, (void *)(&config.bpb.enabled)},
|
|
{16, 0, "btic", "=%i", NULL, (void *)(&config.bpb.btic)},
|
|
{16, 0, "sbp_bnf_fwd", "=%i", NULL, (void *)(&config.bpb.sbp_bnf_fwd)},
|
|
{16, 0, "sbp_bf_fwd", "=%i", NULL, (void *)(&config.bpb.sbp_bf_fwd)},
|
|
{16, 0, "missdelay", "=%i", NULL, (void *)(&config.bpb.missdelay)},
|
|
{16, 0, "hitdelay", "=%i", NULL, (void *)(&config.bpb.hitdelay)}
|
};
|
};
|
|
|
/* *INDENT-ON* */
|
/* *INDENT-ON* */
|
|
|
int current_device = -1;
|
int current_device = -1;
|
