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Rev 992 |
Rev 997 |
Line 47... |
Line 47... |
} ic[MAX_IC_SETS];
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} ic[MAX_IC_SETS];
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void ic_info()
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void ic_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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printf("ICache not implemented. Set UPR[ICP].\n");
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PRINTF("ICache not implemented. Set UPR[ICP].\n");
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return;
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return;
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}
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}
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printf("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
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PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
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PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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- increment IC read hit stats,
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- increment IC read hit stats,
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- set 'lru' at this way to config.ic.ustates - 1 and
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- set 'lru' at this way to config.ic.ustates - 1 and
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