URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_69/] [or1ksim/] [sim-config.c] - Diff between revs 847 and 856

Rev 847	Rev 856
Line 83...	Line 83...
`for (i = 0; i < MAX_MEMORIES; i++)`	`for (i = 0; i < MAX_MEMORIES; i++)`
`config.memory.table[i].ce = -1; /* memory is disabled by default */`	`config.memory.table[i].ce = -1; /* memory is disabled by default */`

`/* IMMU & DMMU*/`	`/* IMMU & DMMU*/`
`config.immu.enabled = 0;`	`config.immu.enabled = 0;`
`config.immu.hitdelay = 0;`	`config.immu.hitdelay = 1;`
`config.immu.missdelay = 0;`	`config.immu.missdelay = 1;`
`config.dmmu.enabled = 0;`	`config.dmmu.enabled = 0;`
`config.dmmu.hitdelay = 0;`	`config.dmmu.hitdelay = 1;`
`config.dmmu.missdelay = 0;`	`config.dmmu.missdelay = 1;`

`/* IC & DC */`	`/* IC & DC */`
`config.ic.enabled = 0;`	`config.ic.enabled = 0;`
`config.ic.hitdelay = 0;`	`config.ic.hitdelay = 1;`
`config.ic.missdelay = 0;`	`config.ic.missdelay = 1;`
`config.ic.nways = 0;`	`config.ic.nways = 0;`
`config.ic.nsets = 0;`	`config.ic.nsets = 0;`
`config.ic.ustates = 0;`	`config.ic.ustates = 0;`
`config.dc.enabled = 0;`	`config.dc.enabled = 0;`
`config.dc.load_hitdelay = 0;`	`config.dc.load_hitdelay = 2;`
`config.dc.load_missdelay = 0;`	`config.dc.load_missdelay = 2;`
`config.dc.nways = 0;`	`config.dc.nways = 0;`
`config.dc.nsets = 0;`	`config.dc.nsets = 0;`
`config.dc.ustates = 0;`	`config.dc.ustates = 0;`
`config.dc.store_hitdelay = 0;`	`config.dc.store_hitdelay = 0;`
`config.dc.store_missdelay = 0;`	`config.dc.store_missdelay = 0;`