| Line 182... |
Line 182... |
/* Update ITLB miss counter and EA */
|
/* Update ITLB miss counter and EA */
|
itlb_miss_count++;
|
itlb_miss_count++;
|
itlb_miss_ea = ea;
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itlb_miss_ea = ea;
|
|
|
/* Whatever access is in progress, translated address have to point to physical RAM */
|
/* Whatever access is in progress, translated address have to point to physical RAM */
|
ta = (ea & ((FLASH_SIZE/2) - 1)) + TEXT_END_ADD;
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ta = (ea & ((RAM_SIZE/2) - 1)) + DATA_END_ADD;
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tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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printf("ta = %.8lx\n", ta);
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printf("ta = %.8lx\n", ta);
|
|
|
/* Set ITLB entry */
|
/* Set ITLB entry */
|
mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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| Line 548... |
Line 548... |
mtspr (SPR_ITLBMR_BASE(i) + set, 0);
|
mtspr (SPR_ITLBMR_BASE(i) + set, 0);
|
}
|
}
|
|
|
/* Perform jumps to address, that is not in ITLB */
|
/* Perform jumps to address, that is not in ITLB */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
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TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
|
|
|
/* Check if there was ITLB miss */
|
/* Check if there was ITLB miss */
|
ASSERT(itlb_miss_count == (i + 1));
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ASSERT(itlb_miss_count == (i + 1));
|
ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
|
ASSERT(itlb_miss_ea == (RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
|
}
|
}
|
|
|
/* Reset ITLB miss counter and EA */
|
/* Reset ITLB miss counter and EA */
|
itlb_miss_count = 0;
|
itlb_miss_count = 0;
|
itlb_miss_ea = 0;
|
itlb_miss_ea = 0;
|
|
|
/* Perform jumps to address, that is now in ITLB */
|
/* Perform jumps to address, that is now in ITLB */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
|
TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
|
|
|
/* Check if there was ITLB miss */
|
/* Check if there was ITLB miss */
|
ASSERT(itlb_miss_count == 0);
|
ASSERT(itlb_miss_count == 0);
|
}
|
}
|
|
|
| Line 574... |
Line 574... |
mtspr (SPR_ITLBMR_BASE(i) + set, mfspr (SPR_ITLBMR_BASE(i) + set) & ~SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(i) + set, mfspr (SPR_ITLBMR_BASE(i) + set) & ~SPR_ITLBMR_V);
|
}
|
}
|
|
|
/* Perform jumps to address, that is now in ITLB but is invalid */
|
/* Perform jumps to address, that is now in ITLB but is invalid */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
|
TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
|
|
|
/* Check if there was ITLB miss */
|
/* Check if there was ITLB miss */
|
ASSERT(itlb_miss_count == (i + 1));
|
ASSERT(itlb_miss_count == (i + 1));
|
ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
|
ASSERT(itlb_miss_ea == (RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
| Line 594... |
Line 594... |
excpt_buserr = (unsigned long)bus_err_handler;
|
excpt_buserr = (unsigned long)bus_err_handler;
|
|
|
/* Register illegal insn handler */
|
/* Register illegal insn handler */
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
|
|
#if 0
|
#if 1
|
/* Translation test */
|
/* Translation test */
|
dtlb_translation_test ();
|
dtlb_translation_test ();
|
|
|
/* Virtual address match test */
|
/* Virtual address match test */
|
for (j = 0; j < DTLB_WAYS; j++) {
|
for (j = 0; j < DTLB_WAYS; j++) {
|
| Line 609... |
Line 609... |
/* Valid bit testing */
|
/* Valid bit testing */
|
for (i = 1; i < (DTLB_SETS - 1); i++)
|
for (i = 1; i < (DTLB_SETS - 1); i++)
|
dtlb_valid_bit_test (DTLB_SETS - i);
|
dtlb_valid_bit_test (DTLB_SETS - i);
|
#endif
|
#endif
|
|
|
|
#if 1
|
/* Enable IMMU */
|
/* Enable IMMU */
|
immu_enable();
|
immu_enable();
|
|
|
/* Translation test */
|
/* Translation test */
|
itlb_valid_bit_test (DTLB_SETS - 2);
|
itlb_valid_bit_test (DTLB_SETS - 2);
|
|
#endif
|
|
|
report (0xdeaddead);
|
report (0xdeaddead);
|
exit (0);
|
exit (0);
|
return 0;
|
return 0;
|
}
|
}
|
