OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_72/] [or1ksim/] [sim-config.h] - Diff between revs 1308 and 1320

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1308 Rev 1320
Line 288... Line 288...
    int output_cfg;                   /* Whether sim is to output cfg files */
    int output_cfg;                   /* Whether sim is to output cfg files */
    char script_fn[STR_SIZE];         /* Script file read */
    char script_fn[STR_SIZE];         /* Script file read */
    int iprompt;                      /* Interactive prompt */
    int iprompt;                      /* Interactive prompt */
    int cont_run;                     /* Continuos run versus single
    int cont_run;                     /* Continuos run versus single
                                         step tracing switch. */
                                         step tracing switch. */
    int cycles;                       /* Cycles counts fetch stages */
    long long cycles;                 /* Cycles counts fetch stages */
 
 
    int mem_cycles;                   /* Each cycle has counter of mem_cycles;
    int mem_cycles;                   /* Each cycle has counter of mem_cycles;
                                         this value is joined with cycles
                                         this value is joined with cycles
                                         at the end of the cycle; no sim
                                         at the end of the cycle; no sim
                                         originated memory accesses should be
                                         originated memory accesses should be
                                         performed inbetween. */
                                         performed inbetween. */
    int loadcycles;                   /* Load and store stalls */
    int loadcycles;                   /* Load and store stalls */
    int storecycles;
    int storecycles;
 
 
 
    long long reset_cycles;
  } sim;
  } sim;
 
 
  /* Command line parameters */
  /* Command line parameters */
  struct {
  struct {
    int profile;                      /* Whether profiling was enabled */
    int profile;                      /* Whether profiling was enabled */
Line 312... Line 314...
    unsigned long lea;                /* Load effective address */
    unsigned long lea;                /* Load effective address */
    unsigned long sea;                /* Store effective address */
    unsigned long sea;                /* Store effective address */
    unsigned long ld;                 /* Load data */
    unsigned long ld;                 /* Load data */
    unsigned long sd;                 /* Store data */
    unsigned long sd;                 /* Store data */
    unsigned long lsea;               /* Load/Store effective address */
    unsigned long lsea;               /* Load/Store effective address */
    int instructions;                 /* Instructions executed */
    long long instructions;           /* Instructions executed */
 
    long long reset_instructions;
 
 
    int stalled;
    int stalled;
    int hazardwait;                   /* how many cycles were wasted because of hazards */
    int hazardwait;                   /* how many cycles were wasted because of hazards */
    int supercycles;                  /* Superscalar cycles */
    int supercycles;                  /* Superscalar cycles */
  } cpu;
  } cpu;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.