| Line 17... |
Line 17... |
#define UART_FCR (UART_ADDR + 2)
|
#define UART_FCR (UART_ADDR + 2)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_LCR (UART_ADDR + 3)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_MCR (UART_ADDR + 4)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_LSR (UART_ADDR + 5)
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#define UART_MSR (UART_ADDR + 6)
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#define UART_MSR (UART_ADDR + 6)
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|
#define UART_SCR (UART_ADDR + 7)
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|
|
#define UART_DLL (UART_ADDR + 0)
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#define UART_DLL (UART_ADDR + 0)
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#define UART_DLH (UART_ADDR + 1)
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#define UART_DLH (UART_ADDR + 1)
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|
|
#define LCR_DIVL (0x80)
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#define LCR_DIVL (0x80)
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| Line 46... |
Line 47... |
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Waits a few cycles that uart can prepare its data */
|
/* Waits a few cycles that uart can prepare its data */
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
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/* fails if there is an error */
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/* fails if there is an error */
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & (LSR_BREAK|LSR_FE|LSR_PE|LSR_OE)) && !(x & LSR_ERR)) \
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printf ("LSR7 (0x%02x) ERR @ %i\n", x, __LINE__); ASSERT(!(x & LSR_ERR));}
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printf ("LSR7 (0x%02x) ERR @ %i\n", x, __LINE__); ASSERT(!(x & LSR_ERR) && ((x & 0x60) != 0x40));}
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#define MARK() printf ("Passed line %i\n", __LINE__)
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#define MARK() printf ("Passed line %i\n", __LINE__)
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|
|
#ifndef __LINE__
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#ifndef __LINE__
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#define __LINE__ 0
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#define __LINE__ 0
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#endif
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#endif
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| Line 167... |
Line 168... |
ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_MCR) == 0x00); //4
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#if COMPLETE
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#if COMPLETE
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_MSR) == 0x00); //6
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ASSERT(getreg (UART_MSR) == 0x00); //6
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#endif
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#endif
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ASSERT(getreg (UART_SCR) == 0x00); //7
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|
|
setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLH) == 0x00); //1
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ASSERT(getreg (UART_DLH) == 0x00); //1
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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| Line 245... |
Line 247... |
ASSERT(getreg (UART_LCR) == tmp);
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ASSERT(getreg (UART_LCR) == tmp);
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}
|
}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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}
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}
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MARK();
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MARK();
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|
|
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{ /* SCR Test :))) */
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int i;
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|
setreg (UART_SCR, 0);
|
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ASSERT (getreg (UART_SCR) == 0);
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|
setreg (UART_SCR, 0xff);
|
|
ASSERT (getreg (UART_SCR) == 0xff);
|
|
for (i = 0; i < 16; i++) {
|
|
unsigned char tmp = 0xdead << i;
|
|
setreg (UART_SCR, tmp);
|
|
ASSERT (getreg (UART_SCR) == tmp);
|
|
}
|
|
}
|
|
MARK();
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/* Other registers will be tested later, if they function correctly,
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/* Other registers will be tested later, if they function correctly,
|
since we cannot test them now, without destroying anything. */
|
since we cannot test them now, without destroying anything. */
|
}
|
}
|
|
|
/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
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/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
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|
|
void send_recv_test ()
|
void send_recv_test ()
|
{
|
{
|
char *s;
|
char *s;
|
printf ("send_recv_test: ");
|
printf ("send_recv_test\n");
|
/* Init */
|
/* Init */
|
MARK();
|
MARK();
|
|
|
//printf ("basic\n");
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//printf ("basic\n");
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
|
ASSERT (!(getreg (UART_LSR) & LSR_DR));
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| Line 310... |
Line 326... |
|
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void break_test ()
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void break_test ()
|
{
|
{
|
unsigned x;
|
unsigned x;
|
char *s;
|
char *s;
|
printf ("break_test: ");
|
printf ("break_test\n");
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|
|
MARK();
|
MARK();
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/* Send a break */
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/* Send a break */
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NO_ERROR();
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NO_ERROR();
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MARK();
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MARK();
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| Line 399... |
Line 415... |
}
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}
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|
|
void different_modes_test ()
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void different_modes_test ()
|
{
|
{
|
int speed, parity, length;
|
int speed, parity, length;
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printf ("different modes test");
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printf ("different modes test\n");
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init_8n1();
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init_8n1();
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|
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/* Init */
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/* Init */
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MARK();
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MARK();
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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| Line 441... |
Line 457... |
MARK();
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MARK();
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}
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}
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MARK();
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MARK();
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|
|
/* Restore normal mode */
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/* Restore normal mode */
|
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send_char ('T');
|
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while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_LCR, LCR_DIVL);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLH, 2 >> 8);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_DLL, 2 & 0xff);
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setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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MARK();
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MARK();
|
|
|
|
send_char ('T');
|
|
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */
|
|
MARK();
|
printf ("OK\n");
|
printf ("OK\n");
|
}
|
}
|
|
|
/* Test various FIFO levels, break and framing error interrupt, etc */
|
/* Test various FIFO levels, break and framing error interrupt, etc */
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|
|
void interrupt_test ()
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void interrupt_test ()
|
{
|
{
|
int i;
|
int i;
|
printf ("interrupt_test");
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printf ("interrupt_test\n");
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/* Configure UART for interrupt mode */
|
/* Configure UART for interrupt mode */
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
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setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_LCR, LCR_DIVL);
|
setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
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setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
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setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
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setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
|
|
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
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setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
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setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
|
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
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ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
MARK();
|
MARK();
|
| Line 585... |
Line 607... |
while (!int_cnt); /* Wait for break interrupt */
|
while (!int_cnt); /* Wait for break interrupt */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_iir == 0xc6);
|
ASSERT (int_lsr == 0xf9); /* BE flag should be set */
|
ASSERT (int_lsr == 0xf9); /* BE flag should be set */
|
ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
|
ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */
|
|
MARK();
|
recv_char (0);
|
recv_char (0);
|
MARK();
|
MARK();
|
|
|
send_char ('B'); /* Release break */
|
send_char ('B'); /* Release break */
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
| Line 596... |
Line 619... |
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
/* Wait for acknowledge */
|
/* Wait for acknowledge */
|
int_rbr = '$';
|
int_rbr = '$';
|
while (!int_cnt); /* Wait for DR */
|
while (!int_cnt); /* Wait for timeout */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc4);
|
ASSERT (int_iir == 0xcc);
|
ASSERT (int_lsr == 0x61);
|
ASSERT (int_lsr == 0x61);
|
MARK();
|
MARK();
|
|
|
/* TODO: Check for parity error */
|
/* TODO: Check for parity error */
|
/* TODO: Check for frame error */
|
/* TODO: Check for frame error */
|
| Line 622... |
Line 645... |
ASSERT (int_lsr == 0x61); /* DR flag should be set */
|
ASSERT (int_lsr == 0x61); /* DR flag should be set */
|
ASSERT (getreg (UART_LSR) == 0x60); /* DR flag should be cleared - timeout occurred */
|
ASSERT (getreg (UART_LSR) == 0x60); /* DR flag should be cleared - timeout occurred */
|
MARK();
|
MARK();
|
|
|
send_char ('T');
|
send_char ('T');
|
|
while (!int_cnt); /* Wait for THR to be empty */
|
|
ASSERT (--int_cnt == 0);
|
|
ASSERT (int_iir == 0xc2);
|
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
|
MARK();
|
|
|
setreg (UART_IER, 0x00); /* Disable interrupts */
|
setreg (UART_IER, 0x00); /* Disable interrupts */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
ASSERT (int_cnt == 0); /* no interrupts should be pending */
|
|
NO_ERROR ();
|
|
|
|
while (getreg (UART_LSR) != 0x60); /* wait till we sent everynthing and then change mode */
|
|
setreg (UART_LCR, LCR_DIVL);
|
|
setreg (UART_DLH, 2 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
|
setreg (UART_DLL, 2 & 0xff);
|
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
|
send_char ('T');
|
|
|
|
MARK ();
|
|
printf ("OK\n");
|
|
}
|
|
|
|
/* Test if all control bits are set correctly. Lot of this was already tested
|
|
elsewhere and tests are not duplicated. */
|
|
|
|
void control_register_test ()
|
|
{
|
|
/* RBR already tested in send_recv_test() */
|
|
/* THR already tested in send_recv_test() */
|
|
/* IER already tested in interrupt_test() */
|
|
/* IIR already tested in interrupt_test() */
|
|
/* FCR0 - uart 16450 specific, not tested */
|
|
|
|
/* FCR1 - reset rx FIFO */
|
|
send_char ('*');
|
|
NO_ERROR ();
|
|
while (!(getreg (UART_LSR) & 0x01)); /* Wait for data ready */
|
|
setreg (UART_FCR, 2); /* Clears rx fifo */
|
|
ASSERT (getreg (UART_LSR) == 0x60); /* nothing happening */
|
|
send_char ('!');
|
|
recv_char ('!');
|
|
MARK ();
|
|
|
|
/* FCR2 - reset tx FIFO */
|
|
send_char ('1');
|
|
send_char ('2');
|
|
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
|
|
ASSERT (getreg (UART_LSR) == 0x00); /* we should still be sending '1' */
|
|
NO_ERROR();
|
|
send_char ('*');
|
|
recv_char ('*');
|
|
MARK ();
|
|
|
|
/* LCR already tested in different_modes_test () */
|
|
/* TODO: MSR */
|
|
/* LSR already tested in different_modes_test () and interrupt_test() */
|
|
/* SCR already tested in register_test () */
|
|
|
|
MARK ();
|
|
printf ("OK\n");
|
|
}
|
|
|
|
/* Tests parity error and frane error behaviour */
|
|
|
|
void line_error_test ()
|
|
{
|
|
printf ("line_error_test\n");
|
|
|
|
/* Test framing error if we change speed */
|
|
setreg (UART_LCR, LCR_DIVL);
|
|
setreg (UART_DLH, 2 >> 8);
|
|
setreg (UART_DLL, 2 & 0xff);
|
|
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */
|
|
MARK();
|
|
|
|
send_char ('c');
|
|
ASSERT (int_cnt == 0);
|
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
|
while (!int_cnt); /* Wait for THR to be empty */
|
|
ASSERT (--int_cnt == 0);
|
|
ASSERT (int_iir == 0xc6);
|
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
|
getreg (UART_RBR); /* Ignore the data */
|
|
MARK ();
|
|
recv_char ('b');
|
|
MARK ();
|
|
|
|
#if COMPLETE
|
|
/* Test framing error if we change stop bits */
|
|
send_char ('*');
|
|
while (getreg (UART_LSR)); /* wait till we sent everynthing and then change mode */
|
|
setreg (UART_LCR, 0x07); /* 8N2 */
|
|
send_char ('*');
|
|
MARK ();
|
|
|
/* TODO: check if trigger is set up on full fifo */
|
ASSERT (int_cnt == 0);
|
|
setreg (UART_IER, 0x04); /* Enable interrupts: line status */
|
|
while (!int_cnt); /* Wait for THR to be empty */
|
|
ASSERT (--int_cnt == 0);
|
|
ASSERT (int_iir == 0xc6);
|
|
ASSERT (int_lsr == 0xe9); /* Framing error and FIFO error */
|
|
getreg (UART_RBR); /* Ignore the data */
|
|
recv_char ('b');
|
|
MARK();
|
|
#endif
|
|
|
MARK ();
|
MARK ();
|
|
printf ("OK\n");
|
}
|
}
|
|
|
int main ()
|
int main ()
|
{
|
{
|
/* Use our low priority interrupt handler */
|
/* Use our low priority interrupt handler */
|
| Line 640... |
Line 763... |
|
|
/* Enable interrupts */
|
/* Enable interrupts */
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR | SPR_SR_EIR);
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR | SPR_SR_EIR);
|
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
|
|
// register_test ();
|
register_test ();
|
init_8n1 ();
|
init_8n1 ();
|
// send_recv_test ();
|
// send_recv_test ();
|
// break_test ();
|
// break_test ();
|
// different_modes_test ();
|
// different_modes_test ();
|
interrupt_test ();
|
// interrupt_test ();
|
/*control_register_test ();
|
// control_register_test ();
|
loopback_send_rcv_test ();
|
line_error_test ();
|
fifo_test ();
|
|
loopback_test ();
|
/* loopback_test ();
|
modem_test ();
|
modem_test ();
|
line_error_test ();
|
|
speed_error_test ();
|
|
frame_error_test ();
|
|
modem_error_test ();*/
|
modem_error_test ();*/
|
|
recv_char ('@');
|
printf ("ALL TESTS PASSED\n");
|
printf ("ALL TESTS PASSED\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
