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[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1302 and 1308

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Rev 1302 Rev 1308
Line 24... Line 24...
 
 
#include "arch.h"
#include "arch.h"
#include "sprs.h"
#include "sprs.h"
#include "abstract.h"
#include "abstract.h"
#include "sim-config.h"
#include "sim-config.h"
 
#include "except.h"
 
 
extern int flag;
extern int flag;
 
 
sprword sprs[MAX_SPRS];
sprword sprs[MAX_SPRS];
 
 
Line 58... Line 59...
  case SPR_NPC:
  case SPR_NPC:
    {
    {
      extern unsigned long pc;
      extern unsigned long pc;
      extern unsigned long pcnext;
      extern unsigned long pcnext;
      extern int delay_insn;
      extern int delay_insn;
      extern unsigned long pcdelay;
 
 
 
      clear_pending_exception ();
      clear_pending_exception ();
 
 
      /* The debugger has redirected us to a new address */
      /* The debugger has redirected us to a new address */
      /* This is usually done to reissue an instruction
      /* This is usually done to reissue an instruction
Line 134... Line 134...
}
}
 
 
/* Show status of important SPRs. */
/* Show status of important SPRs. */
void sprs_status()
void sprs_status()
{
{
  PRINTF("VR   : 0x%.8x  UPR  : 0x%.8x\n", mfspr(SPR_VR), mfspr(SPR_UPR));
  PRINTF("VR   : 0x%.8lx  UPR  : 0x%.8lx\n", mfspr(SPR_VR), mfspr(SPR_UPR));
  PRINTF("SR   : 0x%.8x\n", mfspr(SPR_SR));
  PRINTF("SR   : 0x%.8lx\n", mfspr(SPR_SR));
  PRINTF("MACLO: 0x%.8x  MACHI: 0x%.8x\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI));
  PRINTF("MACLO: 0x%.8lx  MACHI: 0x%.8lx\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI));
  PRINTF("EPCR0: 0x%.8x  EPCR1: 0x%.8x\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1));
  PRINTF("EPCR0: 0x%.8lx  EPCR1: 0x%.8lx\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1));
  PRINTF("EEAR0: 0x%.8x  EEAR1: 0x%.8x\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1));
  PRINTF("EEAR0: 0x%.8lx  EEAR1: 0x%.8lx\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1));
  PRINTF("ESR0 : 0x%.8x  ESR1 : 0x%.8x\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1));
  PRINTF("ESR0 : 0x%.8lx  ESR1 : 0x%.8lx\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1));
  PRINTF("TTMR : 0x%.8x  TTCR : 0x%.8x\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR));
  PRINTF("TTMR : 0x%.8lx  TTCR : 0x%.8lx\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR));
  PRINTF("PICMR: 0x%.8x  PICSR: 0x%.8x\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR));
  PRINTF("PICMR: 0x%.8lx  PICSR: 0x%.8lx\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR));
  PRINTF("PPC:   0x%.8x  NPC   : 0x%.8x\n", mfspr(SPR_PPC), mfspr(SPR_NPC));
  PRINTF("PPC:   0x%.8lx  NPC   : 0x%.8lx\n", mfspr(SPR_PPC), mfspr(SPR_NPC));
}
}
 
 
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