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Line 29... |
#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "except.h"
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#include "except.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "icache_model.h"
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#include "icache_model.h"
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extern int flag;
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sprword sprs[MAX_SPRS];
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extern int flag;
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int audio_cnt = 0;
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int audio_cnt = 0;
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static FILE *fo = 0;
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static FILE *fo = 0;
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/* Set a specific SPR with a value. */
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/* Set a specific SPR with a value. */
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inline void
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inline void
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mtspr(uint16_t regno, const sprword value)
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mtspr(uint16_t regno, const sprword value)
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{
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{
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regno %= MAX_SPRS;
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regno %= MAX_SPRS;
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sprs[regno] = value;
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cpu_state.sprs[regno] = value;
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/* MM: Register hooks. */
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/* MM: Register hooks. */
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switch (regno) {
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switch (regno) {
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case SPR_TTCR:
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case SPR_TTCR:
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spr_write_ttcr (value);
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spr_write_ttcr (value);
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| Line 62... |
Line 63... |
break;
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break;
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/* Data cache simulateing stuff */
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/* Data cache simulateing stuff */
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case SPR_DCBPR:
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case SPR_DCBPR:
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if(value) {
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if(value) {
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dc_simulate_read(value, 4);
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dc_simulate_read(value, 4);
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sprs[SPR_DCBPR] = 0;
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cpu_state.sprs[SPR_DCBPR] = 0;
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}
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}
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break;
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break;
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case SPR_DCBFR:
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case SPR_DCBFR:
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if(value != -1) {
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if(value != -1) {
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dc_inv(value);
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dc_inv(value);
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sprs[SPR_DCBFR] = -1;
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cpu_state.sprs[SPR_DCBFR] = -1;
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}
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}
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break;
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break;
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case SPR_DCBIR:
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case SPR_DCBIR:
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if(value != 0) {
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if(value != 0) {
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dc_inv(value);
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dc_inv(value);
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sprs[SPR_DCBIR] = 0;
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cpu_state.sprs[SPR_DCBIR] = 0;
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}
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}
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break;
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break;
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case SPR_DCBWR:
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case SPR_DCBWR:
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sprs[SPR_DCBWR] = 0;
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cpu_state.sprs[SPR_DCBWR] = 0;
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break;
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break;
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case SPR_DCBLR:
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case SPR_DCBLR:
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sprs[SPR_DCBLR] = 0;
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cpu_state.sprs[SPR_DCBLR] = 0;
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break;
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break;
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/* Instruction cache simulateing stuff */
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/* Instruction cache simulateing stuff */
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case SPR_ICBPR:
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case SPR_ICBPR:
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if(value) {
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if(value) {
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ic_simulate_fetch(value);
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ic_simulate_fetch(value);
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sprs[SPR_ICBPR] = 0;
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cpu_state.sprs[SPR_ICBPR] = 0;
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}
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}
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break;
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break;
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case SPR_ICBIR:
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case SPR_ICBIR:
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if(value) {
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if(value) {
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ic_inv(value);
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ic_inv(value);
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sprs[SPR_ICBIR] = 0;
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cpu_state.sprs[SPR_ICBIR] = 0;
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}
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}
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break;
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break;
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case SPR_ICBLR:
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case SPR_ICBLR:
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sprs[SPR_ICBLR] = 0;
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cpu_state.sprs[SPR_ICBLR] = 0;
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break;
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break;
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case SPR_SR:
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case SPR_SR:
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/* Set internal flag also */
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/* Set internal flag also */
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if(value & SPR_SR_F) flag = 1;
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if(value & SPR_SR_F) flag = 1;
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else flag = 0;
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else flag = 0;
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sprs[regno] |= SPR_SR_FO;
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cpu_state.sprs[regno] |= SPR_SR_FO;
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break;
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break;
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case SPR_NPC:
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case SPR_NPC:
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{
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{
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extern int delay_insn;
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/* The debugger has redirected us to a new address */
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/* The debugger has redirected us to a new address */
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/* This is usually done to reissue an instruction
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/* This is usually done to reissue an instruction
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which just caused a breakpoint exception. */
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which just caused a breakpoint exception. */
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pc = value;
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cpu_state.pc = value;
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if(!value && config.sim.verbose)
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if(!value && config.sim.verbose)
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PRINTF("WARNING: PC just set to 0!\n");
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PRINTF("WARNING: PC just set to 0!\n");
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/* Clear any pending delay slot jumps also */
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/* Clear any pending delay slot jumps also */
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delay_insn = 0;
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cpu_state.delay_insn = 0;
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pcnext = value + 4;
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pcnext = value + 4;
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}
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}
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break;
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break;
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case 0xFFFD:
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case 0xFFFD:
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fo = fopen ("audiosim.pcm", "wb+");
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fo = fopen ("audiosim.pcm", "wb+");
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| Line 150... |
Line 149... |
break;
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break;
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default:
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default:
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/* Mask reseved bits in DTLBMR and DTLBMR registers */
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/* Mask reseved bits in DTLBMR and DTLBMR registers */
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if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
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if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
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if((regno & 0xff) < 0x80)
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if((regno & 0xff) < 0x80)
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sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
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(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
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(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
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else
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else
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sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
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(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
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(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
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SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
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SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
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SPR_DTLBTR_SWE));
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SPR_DTLBTR_SWE));
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}
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}
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/* Mask reseved bits in ITLBMR and ITLBMR registers */
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/* Mask reseved bits in ITLBMR and ITLBMR registers */
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if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
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if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
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if((regno & 0xff) < 0x80)
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if((regno & 0xff) < 0x80)
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sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
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(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
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else
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else
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sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
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(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
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SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
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SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
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}
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}
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/* Links to GPRS */
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/* Links to GPRS */
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if(regno >= 0x0400 && regno < 0x0420) {
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if(regno >= 0x0400 && regno < 0x0420) {
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extern uorreg_t reg[32];
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cpu_state.reg[regno - 0x0400] = value;
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reg[regno - 0x0400] = value;
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}
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}
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break;
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break;
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}
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}
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}
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}
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