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Line 37... |
#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "icache_model.h"
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#include "icache_model.h"
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#include "debug.h"
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DECLARE_DEBUG_CHANNEL(immu);
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extern int flag;
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extern int flag;
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int audio_cnt = 0;
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int audio_cnt = 0;
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static FILE *fo = 0;
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static FILE *fo = 0;
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/* Set a specific SPR with a value. */
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/* Set a specific SPR with a value. */
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inline void
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void
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mtspr(uint16_t regno, const sprword value)
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mtspr(uint16_t regno, const sprword value)
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{
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{
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sprword prev_val;
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regno %= MAX_SPRS;
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regno %= MAX_SPRS;
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prev_val = cpu_state.sprs[regno];
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cpu_state.sprs[regno] = value;
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cpu_state.sprs[regno] = value;
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/* MM: Register hooks. */
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/* MM: Register hooks. */
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switch (regno) {
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switch (regno) {
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case SPR_TTCR:
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case SPR_TTCR:
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Line 110... |
case SPR_SR:
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case SPR_SR:
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/* Set internal flag also */
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/* Set internal flag also */
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if(value & SPR_SR_F) flag = 1;
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if(value & SPR_SR_F) flag = 1;
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else flag = 0;
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else flag = 0;
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cpu_state.sprs[regno] |= SPR_SR_FO;
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cpu_state.sprs[regno] |= SPR_SR_FO;
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#if DYNAMIC_EXECUTION
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if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) {
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TRACE_(immu)("IMMU just became enabled (%lli).\n", runtime.sim.cycles);
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recheck_immu(IMMU_GOT_ENABLED);
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} else if(!(value & SPR_SR_IME) && (prev_val & SPR_SR_IME)) {
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TRACE_(immu)("Remove counting of mmu hit delay with cycles (%lli)\n",
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runtime.sim.cycles);
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recheck_immu(IMMU_GOT_DISABLED);
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}
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#endif
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break;
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break;
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case SPR_NPC:
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case SPR_NPC:
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{
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{
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/* The debugger has redirected us to a new address */
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/* The debugger has redirected us to a new address */
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/* This is usually done to reissue an instruction
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/* This is usually done to reissue an instruction
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Line 175... |
SPR_DTLBTR_SWE));
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SPR_DTLBTR_SWE));
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}
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}
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/* Mask reseved bits in ITLBMR and ITLBMR registers */
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/* Mask reseved bits in ITLBMR and ITLBMR registers */
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if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
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if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
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TRACE_(immu)("Writting to an mmu way (reg: %"PRIx16", value: %"PRIx32")\n",
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regno, value);
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if((regno & 0xff) < 0x80)
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if((regno & 0xff) < 0x80)
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
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(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
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else
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else
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
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(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
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(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
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SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
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SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
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#if DYNAMIC_EXECUTION
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IME) {
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/* The immu got reconfigured. Recheck if the current page in execution
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* is resident in the immu ways. This check would be done during the
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* instruction fetch but since the dynamic execution model does not do
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* instruction fetchs, do it now. */
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recheck_immu(0);
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}
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#endif
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}
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}
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/* Links to GPRS */
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/* Links to GPRS */
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if(regno >= 0x0400 && regno < 0x0420) {
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if(regno >= 0x0400 && regno < 0x0420) {
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cpu_state.reg[regno - 0x0400] = value;
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cpu_state.reg[regno - 0x0400] = value;
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