| Line 66... |
Line 66... |
case SPR_TTMR:
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case SPR_TTMR:
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spr_write_ttmr (value);
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spr_write_ttmr (value);
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break;
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break;
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/* Data cache simulateing stuff */
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/* Data cache simulateing stuff */
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case SPR_DCBPR:
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case SPR_DCBPR:
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if(value) {
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/* FIXME: This is not correct. The arch. manual states: "Memory accesses
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/* FIXME: The arch. manual says "DCBPR is written with the effective
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* are not recorded (Unlike load or store instructions) and cannot invoke
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* address" which suggests it is written with a _virtual_ address,
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* any exception". If the physical address is invalid a bus error will be
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* but it seems that the cache sits behind the mmu. How is this
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* generated. Also if the effective address is not resident in the mmu
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* address translated then? */
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* the read will happen from address 0, which is naturally not correct. */
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dc_simulate_read(value, value, 4);
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dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4);
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cpu_state.sprs[SPR_DCBPR] = 0;
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cpu_state.sprs[SPR_DCBPR] = 0;
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}
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break;
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break;
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case SPR_DCBFR:
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case SPR_DCBFR:
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if(value != -1) {
|
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dc_inv(value);
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dc_inv(value);
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cpu_state.sprs[SPR_DCBFR] = -1;
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cpu_state.sprs[SPR_DCBFR] = -1;
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}
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break;
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break;
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case SPR_DCBIR:
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case SPR_DCBIR:
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if(value != 0) {
|
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dc_inv(value);
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dc_inv(value);
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cpu_state.sprs[SPR_DCBIR] = 0;
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cpu_state.sprs[SPR_DCBIR] = 0;
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}
|
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break;
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break;
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case SPR_DCBWR:
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case SPR_DCBWR:
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cpu_state.sprs[SPR_DCBWR] = 0;
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cpu_state.sprs[SPR_DCBWR] = 0;
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break;
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break;
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case SPR_DCBLR:
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case SPR_DCBLR:
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cpu_state.sprs[SPR_DCBLR] = 0;
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cpu_state.sprs[SPR_DCBLR] = 0;
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break;
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break;
|
/* Instruction cache simulateing stuff */
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/* Instruction cache simulateing stuff */
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case SPR_ICBPR:
|
case SPR_ICBPR:
|
if(value) {
|
/* FIXME: The arch manual does not say what happens when an invalid memory
|
/* FIXME: The arch. manual says "ICBPR is written with the effective
|
* location is specified. I guess the same as for the DCBPR register */
|
* address" which suggests it is written with a _virtual_ address,
|
ic_simulate_fetch(peek_into_itlb(value, 1), value);
|
* but it seems that the cache sits behind the mmu. How is this
|
|
* address translated then? */
|
|
ic_simulate_fetch(value, value);
|
|
cpu_state.sprs[SPR_ICBPR] = 0;
|
cpu_state.sprs[SPR_ICBPR] = 0;
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}
|
|
break;
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break;
|
case SPR_ICBIR:
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case SPR_ICBIR:
|
if(value) {
|
|
ic_inv(value);
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ic_inv(value);
|
cpu_state.sprs[SPR_ICBIR] = 0;
|
cpu_state.sprs[SPR_ICBIR] = 0;
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}
|
|
break;
|
break;
|
case SPR_ICBLR:
|
case SPR_ICBLR:
|
cpu_state.sprs[SPR_ICBLR] = 0;
|
cpu_state.sprs[SPR_ICBLR] = 0;
|
break;
|
break;
|
case SPR_SR:
|
case SPR_SR:
|
