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https://opencores.org/ocsvn/or1k/or1k/trunk
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printf("SR : 0x%.8x\n", mfspr(SPR_SR));
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printf("SR : 0x%.8x\n", mfspr(SPR_SR));
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printf("MACLO: 0x%.8x MACHI: 0x%.8x\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI));
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printf("MACLO: 0x%.8x MACHI: 0x%.8x\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI));
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printf("EPCR0: 0x%.8x EPCR1: 0x%.8x\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1));
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printf("EPCR0: 0x%.8x EPCR1: 0x%.8x\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1));
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printf("EEAR0: 0x%.8x EEAR1: 0x%.8x\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1));
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printf("EEAR0: 0x%.8x EEAR1: 0x%.8x\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1));
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printf("ESR0 : 0x%.8x ESR1 : 0x%.8x\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1));
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printf("ESR0 : 0x%.8x ESR1 : 0x%.8x\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1));
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printf("TTMR : 0x%.8x TTCR : 0x%.8x\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR));
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printf("PICMR: 0x%.8x PICPR: 0x%.8x\n", mfspr(SPR_PICMR), mfspr(SPR_PICPR));
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printf("PICSR: 0x%.8x\n", mfspr(SPR_PICSR));
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}
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}
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