| Line 89... |
Line 89... |
extern uorreg_t __op_param1;
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extern uorreg_t __op_param1;
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extern uorreg_t __op_param2;
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extern uorreg_t __op_param2;
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extern uorreg_t __op_param3;
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extern uorreg_t __op_param3;
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/* Helper function. Whenever we escape the recompiled code and there is a
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static inline void save_t_bound(oraddr_t pc)
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* potential that an exception may happen this function must be called */
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static inline void save_t_temporary(void)
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{
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{
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env->t0 = t0;
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int reg;
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env->t1 = t1;
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env->t2 = t2;
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pc = (pc & config.immu.page_offset_mask) / 4;
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reg = env->curr_page->ts_bound[pc];
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if(reg & 0x1f)
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env->reg[reg & 0x1f] = t0;
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if((reg >> 5) & 0x1f)
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env->reg[(reg >> 5) & 0x1f] = t1;
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if((reg >> 10) & 0x1f)
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env->reg[(reg >> 10) & 0x1f] = t2;
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}
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}
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/* Wrapper around do_scheduler. This is needed because op_do_sched must be as
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* small as possible. */
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void do_sched_wrap(void)
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void do_sched_wrap(void)
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{
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{
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save_t_temporary();
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upd_sim_cycles();
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upd_sim_cycles();
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save_t_bound(env->pc - 4);
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do_scheduler();
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do_scheduler();
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}
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}
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/* do_scheduler wrapper for instructions that are in the delay slot */
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/* do_scheduler wrapper for instructions that are in the delay slot */
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void do_sched_wrap_delay(void)
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void do_sched_wrap_delay(void)
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{
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{
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save_t_temporary();
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upd_sim_cycles();
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upd_sim_cycles();
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env->ts_current = 1;
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/* The PC gets set to the location of the jump, but do_sched increments that
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* so pull it back here to point to the right location again. This could be
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* done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled
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* code. */
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//env->pc -= 4;
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do_scheduler();
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do_scheduler();
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env->ts_current = 0;
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}
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}
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void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
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void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
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{
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{
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uint16_t reg;
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uint16_t reg = 0;
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addr &= config.immu.pagesize - 1;
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addr &= config.immu.pagesize - 1;
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addr >>= 2;
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addr >>= 2;
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reg = dp->ts_bound[addr];
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if(addr)
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reg = dp->ts_bound[addr - 1];
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if(reg & 0x1f)
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if(reg & 0x1f)
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t0 = cpu_state.reg[reg & 0x1f];
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t0 = cpu_state.reg[reg & 0x1f];
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if((reg >> 5) & 0x1f)
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if((reg >> 5) & 0x1f)
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| Line 249... |
Line 248... |
env->delay_insn = 1;
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env->delay_insn = 1;
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env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
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env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
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}
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}
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}
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}
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__or_dynop void op_set_ts_current(void)
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{
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env->ts_current = 1;
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}
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__or_dynop void op_add_pc(void)
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__or_dynop void op_add_pc(void)
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{
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{
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/* FIXME: Optimise */
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/* FIXME: Optimise */
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set_pc(get_pc() + OP_PARAM1);
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set_pc(get_pc() + OP_PARAM1);
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}
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}
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__or_dynop void op_nop_exit(void)
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__or_dynop void op_nop_exit(void)
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{
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{
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upd_sim_cycles();
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upd_sim_cycles();
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save_t_temporary();
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op_support_nop_exit();
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op_support_nop_exit();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_reset(void)
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__or_dynop void op_nop_reset(void)
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| Line 277... |
Line 270... |
do_jump(EXCEPT_RESET);
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do_jump(EXCEPT_RESET);
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}
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}
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__or_dynop void op_nop_printf(void)
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__or_dynop void op_nop_printf(void)
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{
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{
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save_t_temporary();
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upd_sim_cycles();
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upd_sim_cycles();
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op_support_nop_printf();
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op_support_nop_printf();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_report(void)
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__or_dynop void op_nop_report(void)
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{
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{
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save_t_temporary();
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upd_sim_cycles();
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upd_sim_cycles();
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op_support_nop_report();
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op_support_nop_report();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_report_imm(void)
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__or_dynop void op_nop_report_imm(void)
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{
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{
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save_t_temporary();
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upd_sim_cycles();
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upd_sim_cycles();
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op_support_nop_report_imm(OP_PARAM1);
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op_support_nop_report_imm(OP_PARAM1);
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}
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}
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__or_dynop void op_analysis(void)
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__or_dynop void op_analysis(void)
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{
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{
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env->iqueue.insn_index = OP_PARAM1;
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env->iqueue.insn_index = OP_PARAM1;
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env->iqueue.insn = OP_PARAM2;
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env->iqueue.insn = OP_PARAM2;
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env->iqueue.insn_addr = get_pc();
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env->iqueue.insn_addr = get_pc();
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save_t_temporary();
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op_support_analysis();
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op_support_analysis();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_move_gpr1_pc_delay(void)
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__or_dynop void op_move_gpr1_pc_delay(void)
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| Line 885... |
Line 874... |
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__or_dynop void op_prep_rfe(void)
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__or_dynop void op_prep_rfe(void)
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{
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{
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env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
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env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
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env->sprs[SPR_PPC] = get_pc();
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env->sprs[SPR_PPC] = get_pc();
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env->ts_current = 1;
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set_pc(env->sprs[SPR_EPCR_BASE] - 4);
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set_pc(env->sprs[SPR_EPCR_BASE] - 4);
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}
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}
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static inline void prep_except(oraddr_t epcr_base)
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static inline void prep_except(oraddr_t epcr_base)
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{
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{
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| Line 916... |
Line 904... |
* Therefore the pc will point to the instruction after the l.sys or l.trap
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* Therefore the pc will point to the instruction after the l.sys or l.trap
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* instruction */
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* instruction */
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__or_dynop void op_prep_sys_delay(void)
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__or_dynop void op_prep_sys_delay(void)
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{
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{
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env->delay_insn = 0;
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env->delay_insn = 0;
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env->ts_current = 1;
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prep_except(get_pc() - 4);
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prep_except(get_pc() - 4);
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set_pc(EXCEPT_SYSCALL - 4);
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set_pc(EXCEPT_SYSCALL - 4);
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}
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}
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__or_dynop void op_prep_sys(void)
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__or_dynop void op_prep_sys(void)
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{
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{
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env->ts_current = 1;
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prep_except(get_pc() + 4);
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prep_except(get_pc() + 4);
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set_pc(EXCEPT_SYSCALL - 4);
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set_pc(EXCEPT_SYSCALL - 4);
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}
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}
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__or_dynop void op_prep_trap_delay(void)
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__or_dynop void op_prep_trap_delay(void)
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{
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{
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env->ts_current = 1;
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env->delay_insn = 0;
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env->delay_insn = 0;
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prep_except(get_pc() - 4);
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prep_except(get_pc() - 4);
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set_pc(EXCEPT_TRAP - 4);
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set_pc(EXCEPT_TRAP - 4);
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}
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}
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__or_dynop void op_prep_trap(void)
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__or_dynop void op_prep_trap(void)
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{
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{
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env->ts_current = 1;
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prep_except(get_pc());
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prep_except(get_pc());
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set_pc(EXCEPT_TRAP - 4);
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set_pc(EXCEPT_TRAP - 4);
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}
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}
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/* FIXME: This `instruction' should be split up like the l.trap and l.sys
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/* FIXME: This `instruction' should be split up like the l.trap and l.sys
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* instructions are done */
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* instructions are done */
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__or_dynop void op_illegal_delay(void)
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__or_dynop void op_illegal_delay(void)
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{
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{
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env->delay_insn = 0;
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env->delay_insn = 0;
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env->ts_current = 1;
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env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
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env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
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do_jump(EXCEPT_ILLEGAL - 4);
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do_jump(EXCEPT_ILLEGAL - 4);
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}
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}
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__or_dynop void op_illegal(void)
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__or_dynop void op_illegal(void)
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