| Line 54... |
Line 54... |
}
|
}
|
} else {
|
} else {
|
load = II_IS_LOAD (f->INSN(ref).index);
|
load = II_IS_LOAD (f->INSN(ref).index);
|
for (i = 0; i < f->nmsched; i++) {
|
for (i = 0; i < f->nmsched; i++) {
|
if (f->msched[i] == ref) break;
|
if (f->msched[i] == ref) break;
|
if (load && (f->mtype[i] & MT_LOAD)
|
if ((load && (f->mtype[i] & MT_LOAD))
|
|| !load && (f->mtype[i] & MT_STORE)) c++;
|
|| (!load && (f->mtype[i] & MT_STORE))) c++;
|
}
|
}
|
}
|
}
|
return c;
|
return c;
|
}
|
}
|
|
|
| Line 123... |
Line 123... |
assert (s);
|
assert (s);
|
while (*s) {
|
while (*s) {
|
if (*s <= MAX_OPERANDS) {
|
if (*s <= MAX_OPERANDS) {
|
char t[30];
|
char t[30];
|
sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
|
sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
|
} else if (*s == '\b') sprintf (tmp, "%s%i", b);
|
} else if (*s == '\b') sprintf (tmp, "%s%i", tmp, b);
|
else sprintf (tmp, "%s%c", tmp, *s);
|
else sprintf (tmp, "%s%c", tmp, *s);
|
s++;
|
s++;
|
}
|
}
|
GEN ("%-40s /* %s */\n", tmp, ii->disasm);
|
GEN ("%-40s /* %s */\n", tmp, ii->disasm);
|
if (ii->type & IT_MEMORY) {
|
if (ii->type & IT_MEMORY) {
|
| Line 171... |
Line 171... |
REF_BB (ii->op[1]), REF_I (ii->op[1]));
|
REF_BB (ii->op[1]), REF_I (ii->op[1]));
|
}
|
}
|
}
|
}
|
|
|
/* Outputs binary number */
|
/* Outputs binary number */
|
static char *bin_str (unsigned long x, int len)
|
/*
|
{
|
static char *bin_str (unsigned long x, int len)
|
static char bx[33];
|
{
|
char *s = bx;
|
static char bx[33];
|
while (len > 0) *s++ = '0' + ((x >> --len) & 1);
|
char *s = bx;
|
*s = '\0';
|
while (len > 0) *s++ = '0' + ((x >> --len) & 1);
|
return bx;
|
*s = '\0';
|
}
|
return bx;
|
|
}
|
|
*/
|
|
|
/* Returns index of branch instruction inside a block b */
|
/* Returns index of branch instruction inside a block b */
|
static int branch_index (cuc_bb *bb)
|
static int branch_index (cuc_bb *bb)
|
{
|
{
|
int i;
|
int i;
|
| Line 591... |
Line 593... |
switch (j) {
|
switch (j) {
|
case 0: c = 'l'; s = "Load"; break;
|
case 0: c = 'l'; s = "Load"; break;
|
case 1: c = 's'; s = "Store"; break;
|
case 1: c = 's'; s = "Store"; break;
|
case 2: c = 'c'; s = "Calls"; break;
|
case 2: c = 'c'; s = "Calls"; break;
|
}
|
}
|
if (j == 0 && nloads
|
if ((j == 0 && nloads)
|
|| j == 1 && nstores
|
|| (j == 1 && nstores)
|
|| j == 2 && ncalls) {
|
|| (j == 2 && ncalls)) {
|
int cur = 0;
|
int cur = 0;
|
char t[30];
|
char t[30];
|
|
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("always @(");
|
GEN ("always @(");
|
| Line 610... |
Line 612... |
if (nstores) GEN (" or s_end");
|
if (nstores) GEN (" or s_end");
|
GEN (")\n");
|
GEN (")\n");
|
GEN ("begin\n ");
|
GEN ("begin\n ");
|
cucdebug (1, "%s\n", s);
|
cucdebug (1, "%s\n", s);
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (j == 0 && f->mtype[i] & MT_LOAD
|
if ((j == 0 && f->mtype[i] & MT_LOAD)
|
|| j == 1 && f->mtype[i] & MT_STORE
|
|| (j == 1 && f->mtype[i] & MT_STORE)
|
|| j == 2 && f->mtype[i] & MT_CALL) {
|
|| (j == 2 && f->mtype[i] & MT_CALL)) {
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN ("if (");
|
GEN ("if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
| Line 974... |
Line 976... |
/* start/end signals */
|
/* start/end signals */
|
GEN ("\n\n/* start/end signals */\n");
|
GEN ("\n\n/* start/end signals */\n");
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++) {
|
if (log2_int (maxncallees + 1))
|
if (log2_int (maxncallees + 1))
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
log2_int (maxncallees + 1), i, i, i, i, i);
|
log2_int (maxncallees + 1), i, i, i, i);
|
else GEN ("wire i%i_current = 0;\n", i);
|
else GEN ("wire i%i_current = 0;\n", i);
|
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
