OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [sim-config.h] - Diff between revs 1717 and 1718

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1717 Rev 1718
Line 36... Line 36...
  struct {
  struct {
    int enabled;                      /* Is tick timer enabled?  */
    int enabled;                      /* Is tick timer enabled?  */
  } tick;
  } tick;
 
 
  struct {
  struct {
    int enabled;                      /* Whether DMMU is enabled */
 
    int nways;                        /* Number of DTLB ways */
 
    int nsets;                        /* Number of DTLB sets */
 
    int pagesize;                     /* DTLB page size */
 
    int pagesize_log2;                /* DTLB page size (log2(pagesize)) */
 
    oraddr_t page_offset_mask;        /* Address mask to get page offset */
 
    oraddr_t page_mask;               /* Page number mask (diff. from vpn) */
 
    oraddr_t vpn_mask;                /* Address mask to get vpn */
 
    int lru_reload;                   /* What to reload the lru value to */
 
    oraddr_t set_mask;                /* Mask to get set of an address */
 
    int entrysize;                    /* DTLB entry size */
 
    int ustates;                      /* number of DTLB usage states */
 
    int missdelay;                    /* How much cycles does the miss cost */
 
    int hitdelay;                     /* How much cycles does the hit cost */
 
  } dmmu;
 
 
 
  struct {
 
    int enabled;                      /* Whether instruction cache is enabled */
    int enabled;                      /* Whether instruction cache is enabled */
    int nways;                        /* Number of IC ways */
    int nways;                        /* Number of IC ways */
    int nsets;                        /* Number of IC sets */
    int nsets;                        /* Number of IC sets */
    int blocksize;                    /* IC entry size */
    int blocksize;                    /* IC entry size */
    int ustates;                      /* number of IC usage states */
    int ustates;                      /* number of IC usage states */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.