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/* sim-config.h -- Simulator configuration header file
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/* sim-config.h -- Simulator configuration header file
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify it
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it under the terms of the GNU General Public License as published by
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under the terms of the GNU General Public License as published by the Free
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the Free Software Foundation; either version 2 of the License, or
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Software Foundation; either version 3 of the License, or (at your option)
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(at your option) any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful, but WITHOUT
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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GNU General Public License for more details.
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more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License along
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along with this program; if not, write to the Free Software
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#ifndef _CONFIG_H_
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#ifndef _CONFIG_H_
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#define _CONFIG_H_
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#define _CONFIG_H_
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#include <stdio.h>
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#include <stdio.h>
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#endif
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#endif
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} bpb;
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} bpb;
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struct {
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struct {
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unsigned long upr; /* Unit present register */
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unsigned long upr; /* Unit present register */
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unsigned long cfgr; /* CPU configuration register */
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unsigned long ver, rev; /* Version register */
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unsigned long ver, rev; /* Version register */
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int sr; /* Supervision register */
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int sr; /* Supervision register */
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int superscalar; /* superscalara analysis */
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int superscalar; /* superscalara analysis */
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int hazards; /* dependency hazards analysis */
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int hazards; /* dependency hazards analysis */
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int dependstats; /* dependency statistics */
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int dependstats; /* dependency statistics */
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long clkcycle_ps; /* Clock duration in ps */
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long clkcycle_ps; /* Clock duration in ps */
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long system_kfreq; /* System frequency in kHz*/
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long system_kfreq; /* System frequency in kHz*/
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} sim;
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} sim;
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struct {
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struct {
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int enabled; /* Whether is debug module enabled */
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int enabled; /* Is debug module enabled */
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int gdb_enabled; /* Whether is debugging with gdb possible */
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int gdb_enabled; /* Is debugging with gdb possible */
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int server_port; /* A user specified port number for services */
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int server_port; /* A user specified port for services */
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unsigned long vapi_id; /* "Fake" vapi device id for JTAG proxy */
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unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */
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unsigned long int cfgr; /* JPB: Debug config SPR */
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} debug;
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} debug;
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struct { /* Verification API, part of Advanced Core Verification */
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struct { /* Verification API, part of Advanced Core Verification */
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int enabled; /* Whether is VAPI module enabled */
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int enabled; /* Whether is VAPI module enabled */
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int server_port; /* A user specified port number for services */
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int server_port; /* A user specified port number for services */
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