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Line 19... |
more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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INSTRUCTION (l_add) {
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INSTRUCTION (l_add) {
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orreg_t temp1, temp2, temp3;
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orreg_t temp1, temp2, temp3;
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int8_t temp4;
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int8_t temp4;
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temp2 = (orreg_t)PARAM2;
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temp2 = (orreg_t)PARAM2;
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temp3 = (orreg_t)PARAM1;
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temp3 = (orreg_t)PARAM1;
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temp1 = temp2 + temp3;
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temp1 = temp2 + temp3;
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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| Line 54... |
Line 57... |
temp3 = (orreg_t)PARAM1;
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temp3 = (orreg_t)PARAM1;
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temp1 = temp2 + temp3;
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temp1 = temp2 + temp3;
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if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
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if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
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temp1++;
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temp1++;
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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| Line 151... |
Line 154... |
SET_PARAM0(PARAM1 << 16);
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SET_PARAM0(PARAM1 << 16);
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}
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}
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INSTRUCTION (l_and) {
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INSTRUCTION (l_and) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 & PARAM2;
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temp1 = PARAM1 & PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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| Line 163... |
Line 166... |
}
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}
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}
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}
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INSTRUCTION (l_or) {
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INSTRUCTION (l_or) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 | PARAM2;
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temp1 = PARAM1 | PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_xor) {
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INSTRUCTION (l_xor) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 ^ PARAM2;
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temp1 = PARAM1 ^ PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_sub) {
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INSTRUCTION (l_sub) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
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temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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/*int mcount = 0;*/
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/*int mcount = 0;*/
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INSTRUCTION (l_mul) {
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INSTRUCTION (l_mul) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
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temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/*if (!(mcount++ & 1023)) {
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/*if (!(mcount++ & 1023)) {
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PRINTF ("[%i]\n",mcount);
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PRINTF ("[%i]\n",mcount);
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}*/
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}*/
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}
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}
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| Line 200... |
Line 203... |
temp1 = temp2 / temp3;
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temp1 = temp2 / temp3;
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else {
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else {
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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return;
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return;
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}
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}
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_divu) {
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INSTRUCTION (l_divu) {
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uorreg_t temp3, temp2, temp1;
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uorreg_t temp3, temp2, temp1;
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| Line 214... |
Line 217... |
temp1 = temp2 / temp3;
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temp1 = temp2 / temp3;
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else {
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else {
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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return;
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return;
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}
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}
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 16; */
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/* runtime.sim.cycles += 16; */
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}
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}
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INSTRUCTION (l_sll) {
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INSTRUCTION (l_sll) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 << PARAM2;
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temp1 = PARAM1 << PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_sra) {
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INSTRUCTION (l_sra) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 >> PARAM2;
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temp1 = (orreg_t)PARAM1 >> PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_srl) {
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INSTRUCTION (l_srl) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 >> PARAM2;
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temp1 = PARAM1 >> PARAM2;
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set_ov_flag (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_bf) {
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INSTRUCTION (l_bf) {
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if (config.bpb.enabled) {
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if (config.bpb.enabled) {
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| Line 276... |
Line 279... |
next_delay_insn = 1;
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next_delay_insn = 1;
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}
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}
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INSTRUCTION (l_jal) {
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INSTRUCTION (l_jal) {
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cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
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cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
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set_reg(LINK_REGNO, cpu_state.pc + 8);
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setsim_reg(LINK_REGNO, cpu_state.pc + 8);
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next_delay_insn = 1;
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next_delay_insn = 1;
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if (config.sim.profile) {
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if (config.sim.profile) {
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struct label_entry *tmp;
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struct label_entry *tmp;
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if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
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if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
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fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
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fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
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| Line 292... |
Line 295... |
cpu_state.pc_delay);
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cpu_state.pc_delay);
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}
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}
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}
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}
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INSTRUCTION (l_jalr) {
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INSTRUCTION (l_jalr) {
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cpu_state.pc_delay = PARAM0;
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cpu_state.pc_delay = PARAM0;
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set_reg(LINK_REGNO, cpu_state.pc + 8);
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setsim_reg(LINK_REGNO, cpu_state.pc + 8);
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next_delay_insn = 1;
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next_delay_insn = 1;
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}
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}
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INSTRUCTION (l_jr) {
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INSTRUCTION (l_jr) {
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cpu_state.pc_delay = PARAM0;
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cpu_state.pc_delay = PARAM0;
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next_delay_insn = 1;
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next_delay_insn = 1;
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