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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cuc/] [verilog.c] - Diff between revs 1102 and 1103

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Rev 1102 Rev 1103
Line 220... Line 220...
    fprintf (stderr, "Cannot open '%s'\n", tmp);
    fprintf (stderr, "Cannot open '%s'\n", tmp);
    exit (1);
    exit (1);
  }
  }
 
 
  /* output header */
  /* output header */
  GEN ("/* %s -- generated by FLEXelerator\n", tmp);
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
  GEN ("   (C) 2002 Flextronics http://www.flextronics.com/\n");
  GEN ("   (C) 2002 Opencores\n");
  GEN ("   function   \"%s\"\n", funcname);
  GEN ("   function   \"%s\"\n", funcname);
  GEN ("   at         %08x - %08x\n", f->start_addr, f->end_addr);
  GEN ("   at         %08x - %08x\n", f->start_addr, f->end_addr);
  GEN ("   num BBs    %i */\n\n", f->num_bb);
  GEN ("   num BBs    %i */\n\n", f->num_bb);
 
 
  GEN ("`include \"timescale.v\"\n\n");
  GEN ("`include \"timescale.v\"\n\n");
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    GEN ("  else s_dat_o = 32'hx;\n");
    GEN ("  else s_dat_o = 32'hx;\n");
    GEN ("end\n");
    GEN ("end\n");
  }
  }
 
 
  /* Generate load and store state machine */
  /* Generate load and store state machine */
 
#if 0
  GEN ("\n/* Load&store state machine */\n");
  GEN ("\n/* Load&store state machine */\n");
  GEN ("always @(posedge clk or posedge rst)\n");
  GEN ("always @(posedge clk or posedge rst)\n");
  GEN ("  if (rst) begin\n");
  GEN ("  if (rst) begin\n");
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
  GEN ("  end else begin\n");
  GEN ("  end else begin\n");
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
 
    int cur = 0;
    dep_list *dep = f->INSN(f->msched[i]).dep;
    dep_list *dep = f->INSN(f->msched[i]).dep;
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
    GEN ("    if (");
    GEN ("    if (");
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
    GEN (") begin\n");
    GEN (") begin\n");
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    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
    GEN ("    end\n");
    GEN ("    end\n");
  }
  }
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
  GEN ("  end\n");
  GEN ("  end\n");
 
#endif
 
 
  /* Generate state generator machine */
  /* Generate state generator machine */
  for (j = 0; j < 2; j++) {
  for (j = 0; j < 2; j++) {
    char c;
    char c;
    char *s;
    char *s;
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    exit (1);
    exit (1);
  }
  }
 
 
  /* output header */
  /* output header */
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
  GEN ("   (C) 2002 Marko Mlinar */\n\n");
  GEN ("   (C) 2002 Opencores */\n\n");
  GEN ("/* Includes %i functions:", nrf);
  GEN ("/* Includes %i functions:", nrf);
  for (i = 0; i < nfuncs; i++) if (f[i])
  for (i = 0; i < nfuncs; i++) if (f[i])
    GEN ("\n%s", prof_func[i].name);
    GEN ("\n%s", prof_func[i].name);
  GEN (" */\n\n");
  GEN (" */\n\n");
 
 

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