| Line 137... |
Line 137... |
case EXCEPT_IPF:
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case EXCEPT_IPF:
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* In immu_translate except_handle is called with except_handle(..., virtaddr) */
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/* In immu_translate except_handle is called with except_handle(..., virtaddr) */
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/* Add the immu miss delay to the cycle counter */
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/* Add the immu miss delay to the cycle counter */
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if(!immu_ex_from_insn) {
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if(!immu_ex_from_insn) {
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mtspr(SPR_EPCR_BASE, get_pc() - (cpu_state.delay_insn ? 4 : 0));
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cpu_state.sprs[SPR_EPCR_BASE] = get_pc() - (cpu_state.delay_insn ? 4 : 0);
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} else
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} else
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/* This exception came from an l.mtspr instruction in which case the pc
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/* This exception came from an l.mtspr instruction in which case the pc
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* points to the l.mtspr instruction when in acutal fact, it is the next
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* points to the l.mtspr instruction when in acutal fact, it is the next
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* instruction that would have faulted/missed. ea is used instead of
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* instruction that would have faulted/missed. ea is used instead of
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* cpu_state.pc + 4 because in the event that the l.mtspr instruction is
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* cpu_state.pc + 4 because in the event that the l.mtspr instruction is
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* in the delay slot of a page local jump the fault must happen on the
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* in the delay slot of a page local jump the fault must happen on the
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* instruction that was jumped to. This is handled in recheck_immu. */
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* instruction that was jumped to. This is handled in recheck_immu. */
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mtspr(SPR_EPCR_BASE, ea);
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cpu_state.sprs[SPR_EPCR_BASE] = ea;
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run_sched_out_of_line(immu_ex_from_insn);
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run_sched_out_of_line(immu_ex_from_insn);
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/* Save the registers that are in the temporaries */
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/* Save the registers that are in the temporaries */
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if(!cpu_state.ts_current)
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if(!cpu_state.ts_current)
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upd_reg_from_t(cpu_state.pc, !immu_ex_from_insn);
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upd_reg_from_t(cpu_state.pc, !immu_ex_from_insn);
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immu_ex_from_insn = 0;
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immu_ex_from_insn = 0;
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| Line 175... |
Line 175... |
upd_reg_from_t(cpu_state.pc - 4, 0);
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upd_reg_from_t(cpu_state.pc - 4, 0);
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else
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else
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upd_reg_from_t(cpu_state.pc, 0);
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upd_reg_from_t(cpu_state.pc, 0);
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}
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}
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#endif
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#endif
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mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
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cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
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break;
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break;
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/* EPCR is loaded with address of next not-yet-executed instruction */
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/* EPCR is loaded with address of next not-yet-executed instruction */
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case EXCEPT_SYSCALL:
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case EXCEPT_SYSCALL:
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mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0));
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cpu_state.sprs[SPR_EPCR_BASE] = (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0);
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break;
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break;
|
/* These exceptions happen AFTER (or before) an instruction has been
|
/* These exceptions happen AFTER (or before) an instruction has been
|
* simulated, therefore the pc already points to the *next* instruction */
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* simulated, therefore the pc already points to the *next* instruction */
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case EXCEPT_TICK:
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case EXCEPT_TICK:
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case EXCEPT_INT:
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case EXCEPT_INT:
|
mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0));
|
cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
|
#if !(DYNAMIC_EXECUTION)
|
#if !(DYNAMIC_EXECUTION)
|
/* If we don't update the pc now, then it will only happen *after* the next
|
/* If we don't update the pc now, then it will only happen *after* the next
|
* instruction (There would be serious problems if the next instruction just
|
* instruction (There would be serious problems if the next instruction just
|
* happens to be a branch), when it should happen NOW. */
|
* happens to be a branch), when it should happen NOW. */
|
cpu_state.pc = pcnext;
|
cpu_state.pc = pcnext;
|
