| Line 69... |
Line 69... |
const char *except_name(oraddr_t except)
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const char *except_name(oraddr_t except)
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{
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{
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return except_names[except >> 8];
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return except_names[except >> 8];
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}
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}
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#if DYNAMIC_EXECUTION
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/* FIXME: Remove the need for this */
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/* This is needed because immu_translate can be called from do_rfe and do_jump
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* in which case the scheduler does not need to get run. immu_translate can also
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* be called from mtspr in which case the exceptions that it generates happen
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* during an instruction and the scheduler needs to get run. */
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int immu_ex_from_insn = 0;
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#endif
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/* Asserts OR1K exception. */
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/* Asserts OR1K exception. */
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/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at
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/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at
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* other times it may not. */
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* other times it may not. */
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void except_handle(oraddr_t except, oraddr_t ea)
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void except_handle(oraddr_t except, oraddr_t ea)
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{
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{
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| Line 133... |
Line 124... |
case EXCEPT_RESET:
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case EXCEPT_RESET:
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break;
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break;
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/* EPCR is loaded with address of instruction that caused the exception */
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/* EPCR is loaded with address of instruction that caused the exception */
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case EXCEPT_ITLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_IPF:
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case EXCEPT_IPF:
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cpu_state.sprs[SPR_EPCR_BASE] = ea - (cpu_state.delay_insn ? 4 : 0);
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* In immu_translate except_handle is called with except_handle(..., virtaddr) */
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op_join_mem_cycles();
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/* Add the immu miss delay to the cycle counter */
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if(!immu_ex_from_insn) {
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cpu_state.sprs[SPR_EPCR_BASE] = get_pc() - (cpu_state.delay_insn ? 4 : 0);
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} else
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/* This exception came from an l.mtspr instruction in which case the pc
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* points to the l.mtspr instruction when in acutal fact, it is the next
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* instruction that would have faulted/missed. ea is used instead of
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* cpu_state.pc + 4 because in the event that the l.mtspr instruction is
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* in the delay slot of a page local jump the fault must happen on the
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* instruction that was jumped to. This is handled in recheck_immu. */
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cpu_state.sprs[SPR_EPCR_BASE] = ea;
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run_sched_out_of_line(immu_ex_from_insn);
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/* Save the registers that are in the temporaries */
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immu_ex_from_insn = 0;
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break;
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#endif
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#endif
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/* All these exceptions happen during a simulated instruction */
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break;
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case EXCEPT_BUSERR:
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case EXCEPT_BUSERR:
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case EXCEPT_DPF:
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case EXCEPT_DPF:
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case EXCEPT_ALIGN:
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case EXCEPT_ALIGN:
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case EXCEPT_ILLEGAL:
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case EXCEPT_ILLEGAL:
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case EXCEPT_DTLBMISS:
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case EXCEPT_DTLBMISS:
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case EXCEPT_RANGE:
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case EXCEPT_RANGE:
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case EXCEPT_TRAP:
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case EXCEPT_TRAP:
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/* All these exceptions happen during a simulated instruction */
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#if DYNAMIC_EXECUTION
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#if DYNAMIC_EXECUTION
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/* Since these exceptions happen during a simulated instruction and this
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/* Since these exceptions happen during a simulated instruction and this
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* function jumps out to the exception vector the scheduler would never have
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* function jumps out to the exception vector the scheduler would never have
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* a chance to run, therefore run it now */
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* a chance to run, therefore run it now */
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run_sched_out_of_line(1);
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run_sched_out_of_line();
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#endif
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#endif
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cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
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cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
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break;
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break;
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/* EPCR is loaded with address of next not-yet-executed instruction */
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/* EPCR is loaded with address of next not-yet-executed instruction */
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case EXCEPT_SYSCALL:
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case EXCEPT_SYSCALL:
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