| Line 43... |
Line 43... |
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
|
|
// reset the core registers
|
// reset the core registers
|
ata->regs.ctrl = 0x0001;
|
ata->regs.ctrl = 0x0001;
|
ata->regs.stat = (DEV_ID << 28) | (REV << 24);
|
ata->regs.stat = (ata->dev_id << 28) | (ata->rev << 24);
|
ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
|
ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
|
| Line 83... |
Line 83... |
return ata -> regs.stat;
|
return ata -> regs.stat;
|
|
|
case ATA_PCTR :
|
case ATA_PCTR :
|
return ata -> regs.pctr;
|
return ata -> regs.pctr;
|
|
|
#if (DEV_ID > 1)
|
|
case ATA_PFTR0:
|
case ATA_PFTR0:
|
return ata -> regs.pftr0;
|
return ata->dev_id > 1 ? ata->regs.pftr0 : 0;
|
|
|
case ATA_PFTR1:
|
case ATA_PFTR1:
|
return ata -> regs.pftr1;
|
return ata->dev_id > 1 ? ata->regs.pftr1 : 0;
|
#endif
|
|
|
|
#if (DEV_ID > 2)
|
|
case ATA_DTR0 :
|
case ATA_DTR0 :
|
return ata -> regs.dtr0;
|
return ata->dev_id > 2 ? ata->regs.dtr0 : 0;
|
|
|
case ATA_DTR1 :
|
case ATA_DTR1 :
|
return ata -> regs.dtr1;
|
return ata->dev_id > 2 ? ata->regs.dtr1 : 0;
|
|
|
case ATA_RXB :
|
case ATA_RXB :
|
return ata -> regs.rxb;
|
return ata->dev_id > 2 ? ata->regs.rxb : 0;
|
#endif
|
|
|
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
else
|
|
/* check if the controller is enabled */
|
/* check if the controller is enabled */
|
if (ata->regs.ctrl & ATA_IDE_EN)
|
if(ata->regs.ctrl & ATA_IDE_EN) {
|
{
|
|
// make sure simulator uses correct read/write delay timings
|
// make sure simulator uses correct read/write delay timings
|
#if (DEV_ID > 1)
|
if(((addr & 0x7f) == ATA_DR) && ata->dev_id > 1) {
|
if ( (addr & 0x7f) == ATA_DR)
|
if(ata->dev_sel)
|
{
|
adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
|
if (ata->devices.dev)
|
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
|
|
else
|
else
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
|
adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
|
}
|
}
|
else
|
else
|
#endif
|
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
|
|
return ata_devices_read(&ata->devices, addr & 0x7f);
|
return ata_devices_read(&ata->devices, addr & 0x7f);
|
}
|
}
|
return 0;
|
return 0;
|
| Line 193... |
Line 185... |
But when using 'DM'-simulator-command, the screen gets filled with these messages.
|
But when using 'DM'-simulator-command, the screen gets filled with these messages.
|
Thereby eradicating the usefulness of the message
|
Thereby eradicating the usefulness of the message
|
*/
|
*/
|
break;
|
break;
|
}
|
}
|
|
return;
|
}
|
}
|
else
|
|
/* check if the controller is enabled */
|
/* check if the controller is enabled */
|
if (ata->regs.ctrl & ATA_IDE_EN)
|
if(ata->regs.ctrl & ATA_IDE_EN) {
|
{
|
|
// make sure simulator uses correct read/write delay timings
|
// make sure simulator uses correct read/write delay timings
|
#if (DEV_ID > 1)
|
if(((addr & 0x7f) == ATA_DR) && (ata->dev_id > 1)) {
|
if ( (addr & 0x7f) == ATA_DR)
|
if(ata->dev_sel)
|
{
|
adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr1), ata_pio_delay(ata->regs.pftr1));
|
if (ata->devices.dev)
|
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
|
|
else
|
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
|
|
}
|
|
else
|
else
|
#endif
|
adjust_rw_delay(ata->mem, ata_pio_delay(ata->regs.pftr0), ata_pio_delay(ata->regs.pftr0));
|
|
} else
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
|
|
|
|
if((addr & 0x7f) == ATA_DHR)
|
|
ata->dev_sel = value & ATA_DHR_DEV;
|
|
|
ata_devices_write(&ata->devices, addr & 0x7f, value);
|
ata_devices_write(&ata->devices, addr & 0x7f, value);
|
}
|
}
|
}
|
}
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
| Line 225... |
Line 216... |
ata_host *ata = dat;
|
ata_host *ata = dat;
|
|
|
if ( ata->baseaddr == 0 )
|
if ( ata->baseaddr == 0 )
|
return;
|
return;
|
|
|
PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", DEV_ID, ata->baseaddr );
|
PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", ata->dev_id, ata->baseaddr );
|
PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );
|
PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );
|
PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );
|
PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );
|
PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );
|
PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );
|
|
|
#if (DEV_ID > 1)
|
if(ata->dev_id > 1) {
|
PRINTF( "ATA FCTR0 : 0x%08lx\n", ata->regs.pftr0 );
|
PRINTF( "ATA FCTR0 : 0x%08x\n", ata->regs.pftr0 );
|
PRINTF( "ATA FCTR1 : 0x%08lx\n", ata->regs.pftr1 );
|
PRINTF( "ATA FCTR1 : 0x%08x\n", ata->regs.pftr1 );
|
#endif
|
}
|
|
|
#if (DEV_ID > 2)
|
if(ata->dev_id > 2) {
|
PRINTF( "ATA DTR0 : 0x%08lx\n", ata->regs.dtr0 );
|
PRINTF( "ATA DTR0 : 0x%08x\n", ata->regs.dtr0 );
|
PRINTF( "ATA DTR1 : 0x%08lx\n", ata->regs.dtr1 );
|
PRINTF( "ATA DTR1 : 0x%08x\n", ata->regs.dtr1 );
|
PRINTF( "ATA TXD : 0x%08lx\n", ata->regs.txb );
|
PRINTF( "ATA TXD : 0x%08x\n", ata->regs.txb );
|
PRINTF( "ATA RXD : 0x%08lx\n", ata->regs.rxb );
|
PRINTF( "ATA RXD : 0x%08x\n", ata->regs.rxb );
|
#endif
|
}
|
}
|
}
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
/*----------------------------------------------------[ ATA Configuration ]---*/
|
/*----------------------------------------------------[ ATA Configuration ]---*/
|
static void ata_baseaddr(union param_val val, void *dat)
|
static void ata_baseaddr(union param_val val, void *dat)
|
| Line 257... |
Line 248... |
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->irq = val.int_val;
|
ata->irq = val.int_val;
|
}
|
}
|
|
|
|
static void ata_dev_id(union param_val val, void *dat)
|
|
{
|
|
ata_host *ata = dat;
|
|
if(val.int_val < 1 || val.int_val > 3) {
|
|
fprintf(stderr, "Peripheral ATA: Unknown device id %d, useing 1\n",
|
|
val.int_val);
|
|
ata->dev_id = 1;
|
|
return;
|
|
}
|
|
|
|
ata->dev_id = val.int_val;
|
|
}
|
|
|
|
static void ata_rev(union param_val val, void *dat)
|
|
{
|
|
ata_host *ata = dat;
|
|
ata->rev = val.int_val;
|
|
}
|
|
|
static void ata_dev_type0(union param_val val, void *dat)
|
static void ata_dev_type0(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device[0].conf.type = val.int_val;
|
ata->devices.device[0].conf.type = val.int_val;
|
}
|
}
|
| Line 328... |
Line 338... |
exit(-1);
|
exit(-1);
|
}
|
}
|
|
|
memset(new, 0, sizeof(ata_host));
|
memset(new, 0, sizeof(ata_host));
|
new->enabled = 1;
|
new->enabled = 1;
|
|
new->dev_id = 1;
|
|
|
return new;
|
return new;
|
}
|
}
|
|
|
static void ata_sec_end(void *dat)
|
static void ata_sec_end(void *dat)
|
{
|
{
|
| Line 368... |
Line 380... |
struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
|
struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
|
|
|
reg_config_param(sec, "enabled", paramt_int, ata_enabled);
|
reg_config_param(sec, "enabled", paramt_int, ata_enabled);
|
reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
|
reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
|
reg_config_param(sec, "irq", paramt_int, ata_irq);
|
reg_config_param(sec, "irq", paramt_int, ata_irq);
|
|
reg_config_param(sec, "dev_id", paramt_int, ata_dev_id);
|
|
reg_config_param(sec, "rev", paramt_int, ata_rev);
|
|
|
reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
|
reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
|
reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
|
reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
|
reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
|
reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
|
reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
|
reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
|
reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
|
reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
|
