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Line 31... |
#include "arch.h"
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#include "arch.h"
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/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
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/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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#include "debug.h"
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#include "atahost.h"
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#include "atahost.h"
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/* default timing reset values */
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/* default timing reset values */
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#define PIO_MODE0_T1 6
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#define PIO_MODE0_T1 6
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Line 45... |
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TEOC 21
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#define DMA_MODE0_TEOC 21
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DEFAULT_DEBUG_CHANNEL(ata);
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/* reset and initialize ATA host core(s) */
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/* reset and initialize ATA host core(s) */
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static void ata_reset(void *dat)
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static void ata_reset(void *dat)
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->mem, 2, 2 );
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adjust_rw_delay( ata->mem, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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TRACE("Read control register: %"PRIx32"\n", ata->regs.ctrl);
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return ata -> regs.ctrl;
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return ata -> regs.ctrl;
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case ATA_STAT :
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case ATA_STAT :
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return ata -> regs.stat;
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return ata -> regs.stat;
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->mem, 2, 2 );
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adjust_rw_delay( ata->mem, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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TRACE("Writting control register: %"PRIx32"\n", value);
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ata -> regs.ctrl = value;
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ata -> regs.ctrl = value;
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/* check if reset bit set, if so reset ata-devices */
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/* check if reset bit set, if so reset ata-devices */
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if (value & ATA_RST)
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if (value & ATA_RST)
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ata_devices_hw_reset(&ata->devices, 1);
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ata_devices_hw_reset(&ata->devices, 1);
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case ATA_STAT :
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case ATA_STAT :
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ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
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ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
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break;
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break;
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case ATA_PCTR :
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case ATA_PCTR :
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TRACE("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata -> regs.pctr = value;
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ata -> regs.pctr = value;
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break;
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break;
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case ATA_PFTR0:
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case ATA_PFTR0:
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TRACE("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata -> regs.pftr0 = value;
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ata -> regs.pftr0 = value;
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break;
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break;
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case ATA_PFTR1:
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case ATA_PFTR1:
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TRACE("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata -> regs.pftr1 = value;
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ata -> regs.pftr1 = value;
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break;
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break;
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case ATA_DTR0 :
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case ATA_DTR0 :
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ata -> regs.dtr0 = value;
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ata -> regs.dtr0 = value;
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