OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [eth.c] - Diff between revs 1469 and 1486

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1469 Rev 1486
Line 646... Line 646...
  Read a register
  Read a register
*/
*/
uint32_t eth_read32( oraddr_t addr, void *dat )
uint32_t eth_read32( oraddr_t addr, void *dat )
{
{
    struct eth_device *eth = dat;
    struct eth_device *eth = dat;
    addr -= eth->baseaddr;
 
 
 
    switch( addr ) {
    switch( addr ) {
    case ETH_MODER: return eth->regs.moder;
    case ETH_MODER: return eth->regs.moder;
    case ETH_INT_SOURCE: return eth->regs.int_source;
    case ETH_INT_SOURCE: return eth->regs.int_source;
    case ETH_INT_MASK: return eth->regs.int_mask;
    case ETH_INT_MASK: return eth->regs.int_mask;
Line 693... Line 692...
*/
*/
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
{
{
    struct eth_device *eth = dat;
    struct eth_device *eth = dat;
 
 
    addr -= eth->baseaddr;
 
 
 
    switch( addr ) {
    switch( addr ) {
    case ETH_MODER:
    case ETH_MODER:
 
 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
             TEST_FLAG( value, ETH_MODER, RXEN) )
             TEST_FLAG( value, ETH_MODER, RXEN) )
Line 887... Line 884...
}
}
 
 
void eth_sec_end(void *dat)
void eth_sec_end(void *dat)
{
{
  struct eth_device *eth = dat;
  struct eth_device *eth = dat;
 
  struct mem_ops ops;
 
 
  if(!eth->enabled) {
  if(!eth->enabled) {
    free(dat);
    free(dat);
    return;
    return;
  }
  }
 
 
  register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32, dat );
  memset(&ops, 0, sizeof(struct mem_ops));
 
 
 
  ops.readfunc32 = eth_read32;
 
  ops.writefunc32 = eth_write32;
 
  ops.read_dat32 = dat;
 
  ops.write_dat32 = dat;
 
 
 
  /* FIXME: Correct delay? */
 
  ops.delayr = 2;
 
  ops.delayw = 2;
 
  reg_mem_area( eth->baseaddr, ETH_ADDR_SPACE, 0, &ops );
  reg_sim_stat( eth_status, dat );
  reg_sim_stat( eth_status, dat );
  reg_sim_reset( eth_reset, dat );
  reg_sim_reset( eth_reset, dat );
}
}
 
 
void reg_ethernet_sec(void)
void reg_ethernet_sec(void)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.