URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [peripheral/] [memory.c] - Diff between revs 1748 and 1751

Rev 1748	Rev 1751
Line 162...	Line 162...
`simmem_write_null16 (oraddr_t addr, uint16_t value, void *dat)`	`simmem_write_null16 (oraddr_t addr, uint16_t value, void *dat)`
`{`	`{`
`if (config.sim.verbose)`	`if (config.sim.verbose)`
`fprintf (stderr,`	`fprintf (stderr,`
`"WARNING: 16-bit memory write to 0x%" PRIxADDR ", non-write "`	`"WARNING: 16-bit memory write to 0x%" PRIxADDR ", non-write "`
`"memory area (value 0x%08" PRIx32 ").\n", addr, value);`	`"memory area (value 0x%08" PRIx16 ").\n", addr, value);`
`}`	`}`

`static void`	`static void`
`simmem_write_null8 (oraddr_t addr, uint8_t value, void *dat)`	`simmem_write_null8 (oraddr_t addr, uint8_t value, void *dat)`
`{`	`{`
`if (config.sim.verbose)`	`if (config.sim.verbose)`
`fprintf (stderr,`	`fprintf (stderr,`
`"WARNING: 8-bit memory write to 0x%" PRIxADDR ", non-write "`	`"WARNING: 8-bit memory write to 0x%" PRIxADDR ", non-write "`
`"memory area (value 0x%08" PRIx32 ").\n", addr, value);`	`"memory area (value 0x%08" PRIx8 ").\n", addr, value);`
`}`	`}`

`static void`	`static void`
`mem_reset (void *dat)`	`mem_reset (void *dat)`
`{`	`{`