| Line 60... |
Line 60... |
{
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{
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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} else if(cpu_state.sprs[SPR_PICSR] & (1 << (int)dat))
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} else if(cpu_state.sprs[SPR_PICSR] & cpu_state.sprs[SPR_PICMR])
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/* Reschedule only if the interrupt hasn't been cleared */
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/* Reschedule only if the interrupt hasn't been cleared */
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sched_next_insn(pic_clock, dat);
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sched_next_insn(pic_clock, NULL);
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}
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}
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|
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/* WARNING: Don't eaven try and call this function *during* a simulated
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/* WARNING: Don't eaven try and call this function *during* a simulated
|
* instruction!! (as in during a read_mem or write_mem callback). except_handle
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* instruction!! (as in during a read_mem or write_mem callback). except_handle
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* assumes that this is the case, it breaks otherwise. */
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* assumes that this is the case, it breaks otherwise. */
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| Line 79... |
Line 79... |
cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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|
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TRACE("Asserting interrupt %d (%s).\n", line,
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TRACE("Asserting interrupt %d (%s).\n", line,
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(cpu_state.sprs[SPR_PICMR] & (1 << line)) ? "Unmasked" : "Masked");
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(cpu_state.sprs[SPR_PICMR] & (1 << line)) ? "Unmasked" : "Masked");
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|
|
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SCHED_FIND_REMOVE(pic_clock, NULL);
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|
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if ((cpu_state.sprs[SPR_PICMR] & (1 << line)) || line < 2) {
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if ((cpu_state.sprs[SPR_PICMR] & (1 << line)) || line < 2) {
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cpu_state.sprs[SPR_PICSR] |= 1 << line;
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cpu_state.sprs[SPR_PICSR] |= 1 << line;
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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} else
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return;
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/* Interrupts not currently enabled, retry next clock cycle */
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}
|
sched_next_insn(pic_clock, (void *)line);
|
|
}
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}
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|
|
|
if(cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR])
|
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/* Interrupts not currently enabled, retry next clock cycle */
|
|
sched_next_insn(pic_clock, NULL);
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}
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}
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No newline at end of file
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No newline at end of file
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